Fuji Electric Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Fuji Electric Device Technology Co., Ltd.

National Institute of Advanced Industrial Science

Yasuyuki Hoshi

Yuichi Harada

Yuichi Hashizume

Keishirou Kumada

Akimasa Kinoshita

Yasuhiko Oonishi

Takashi Shiigi

Shinsuke Harada

Noriyuki Iwamuro

Yoshihisa Suzuki

Shoji Yamada

Masahito Otsuki

Masanobu Iwaya

Yasushi Miyasaka

Yoshiyuki Sakai

Toshiyuki Matsui

Shingo Hayashi

Mina Ryo

Shin'ichi Nakamata

Yasuyuki Kobayashi

A silicon carbide semiconductor device has a first semiconductor region of a first conductivity type, provided in a semiconductor substrate, spanning an active region and a termination region. A second semiconductor region of a second conductivity type is provided between a first main surface and the first semiconductor region, in the active region. A device structure having a first pn junction is provided between the first and second semiconductor regions. An outer peripheral portion of the active region is provided between the first main surface and the first semiconductor region in the active region, and constitutes a second-conductivity-type outer peripheral region that surrounds a periphery of the device structure and forms a second pn junction with the first semiconductor region. A first protective film is provided on the first main surface. The first protective film blocks light generated by a forward current passing through the first and second pn junctions.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

An active region has, in a periphery thereof, a p-type outer peripheral region that has sequentially from a front surface of a semiconductor substrate, a p-type contact extension portion, a p-type base extension portion, and an upper portion and a lower portion of a p-type extension portion, so as to form, at an outer end portion thereof, steps that are recessed stepwise toward a center of the active region and that in a depth direction, are arranged in ascending order of proximity thereof to the center. An innermost JTE region configuring a voltage withstanding structure contacts an outer end portion of the contact extension portion. Beneath the JTE region, a p-type embedded region is provided at a same depth as the lower portion of the extension portion so as to be apart from the JTE region and the outer peripheral region and surround the periphery of the active region.

Silicon carbide semiconductor device

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10/cmto 9×10/cm. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p-type high-concentration region is provided. Each p-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

Semiconductor device

A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed.

Semiconductor circuit device

A source pad of a main semiconductor element is electrically connected to an n-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.

A semiconductor device includes a first MOS structure portion that includes, as its elements, a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first second-semiconductor-layer of a second conductivity type, first semiconductor regions of the first conductivity type, and first gate insulating films, and a second MOS structure portion that includes, as its elements, the substrate, the first semiconductor layer, a second second-semiconductor-layer, second first-semiconductor-regions of the first conductivity type, and second gate insulating films. First and second portions include all of the elements of the first and second MOS structure portions other than the first and second first-semiconductor-regions and the first and second gate insulating films, respectively. A structure of one of the elements of the first portion is not identical to a structure of a corresponding element of the second portion.

A main semiconductor device element has first and second p-type high-concentration regions that mitigate electric field applied to bottoms of trenches. The first p-type high-concentration regions are provided separate from p-type base regions, face the bottoms of the trenches in a depth direction, and extend in a linear shape in a first direction that is a same direction in which the trenches extend. Between adjacent trenches of the trenches, the second p-type high-concentration regions are provided scattered in the first direction, separate from the first p-type high-concentration regions and the trenches and in contact with the p-type base regions. Between the second p-type high-concentration regions adjacent to one another in the first direction, n-type current spreading regions or n-type high-concentration regions having an impurity concentration higher than that of the n-type current spreading regions are provided in contact with the second p-type high-concentration regions.

A semiconductor device having, in a plan view thereof, an active region and a termination region that surrounds a periphery of the active region. The device includes a semiconductor substrate containing a wide bandgap semiconductor, a first-conductivity-type region provided in the semiconductor substrate, spanning from the active region to the termination region, a plurality of second-conductivity-type regions provided between the first-conductivity-type region and the first main surface of the semiconductor substrate in the active region, a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the second-conductivity-type regions, a second electrode provided on the second main surface of the semiconductor substrate and electrically connected to the first-conductivity-type region, and a lifetime killer region provided in the first-conductivity-type region and spanning from the active region to the termination region. In the active region, pn junctions between the first-conductivity-type region and the second-conductivity-type regions form a vertical semiconductor device element.

Semiconductor device with a lifetime killer region in the substrate

A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.

Semiconductor device and method of manufacturing semiconductor device

A main semiconductor device element is a vertical MOSFET with a trench gate structure, containing silicon carbide as a semiconductor material, and having first and second p-type regions that mitigate electric field applied to bottoms of trenches. The first p-type regions are provided separate from the p-type base regions and face the bottoms of the trenches in a depth direction. The first p-type regions are disposed at an interval that is at most 1.0 &#x3bc;m, in a first direction that is a direction in which gate electrodes extend. The second p-type regions are provided between adjacent trenches of the trenches, separate from the first p-type regions and the trenches, and in contact with the p-type base regions. In the first direction that is the direction in which the trenches, the second p-type regions extend in a linear shape having a length that is substantially equal to that of the trenches.

A semiconductor device includes an active region, a gate ring region surrounding a periphery of the active region, and a source ring region surrounding a periphery of the gate ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a second electrode. The semiconductor device has, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film and a first first-electrode, and has, in the source ring region, a third semiconductor region and a second first-electrode. In the source ring region, a second semiconductor region of the first or second conductivity type is provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device.

A semiconductor device includes a MOS structure part and first to third temperature sensing portions. The MOS structure part has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, and gate electrodes provided in the trenches via a gate insulating film. The first to the third temperature sensing portions are provided in plural and each includes the semiconductor substrate, the first semiconductor layer, a temperature sensing trench, a first polysilicon layer of the first conductivity type and a second polysilicon layer of the second conductivity type provided in the temperature sensing trench via an insulating film, a cathode electrode connected to the first polysilicon layer, and an anode electrode connected to the second polysilicon layer.

Semiconductor device having temperature sensing portions and method of manufacturing the same

A semiconductor device includes an active region configured by a first MOS structure region and a second MOS structure region, a gate ring region surrounding a periphery of the active region, a first ring region surrounding a periphery of the gate ring region, a second ring region surrounding a periphery of the first ring region, and a termination region surrounding a periphery of the second ring region. The semiconductor device has first first-electrodes in the first MOS structure region, second first-electrodes in the second MOS structure region, a third first-electrode in the first ring region, and a fourth first-electrode in the second ring region. The third first-electrode has a potential equal to that of the second first-electrodes, and the fourth first-electrode has a potential equal to that of the first first-electrodes.

Growing community of inventors

Matsumoto, Japan

Yasuyuki Hoshi