Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Fujitsu Semiconductor Limited

Fujitsu Corporation

Socionext Inc.

Yasuyuki Eguchi

Shinya Fujioka

Katsuhiko Hoya

Yoshiaki Okuyama

Jin Kashiwagi

Hideaki Yamazaki

Atsushi Sukeno

Koutoku Sato

According to one embodiment, a memory system is provided with a memory cell array, a first command issuing circuit and a controller. The memory cell array includes a plurality of data areas and a plurality of first parity areas. The data areas are arranged in a plurality of banks or in a plurality of chips, and individually store a plurality of data portions constituting access-unit data. The first parity areas are adjacent to the data areas and individually store a plurality of first parity portions constituting the first parity corresponding to the data. The first command issuing circuit issues a first command for the data areas and the first parity areas. The controller accesses the data areas and the first parity areas in response to the first command.

Memory system

According to one embodiment, a memory system comprises a memory array, a first ECC control circuit, and a second ECC control circuit. The memory cell array stores data, a first parity generated in association with the data based on a first error correction code (ECC) scheme, and a second parity generated in association with the data and the first parity based on a second error correction code (ECC) scheme. The first ECC control circuit executes error correction using the first ECC scheme and the first parity during a read operation on the memory cell array. The second ECC control circuit executes error correction using the second ECC scheme and the second parity during a scrub operation on the memory cell array. The first ECC scheme and the second ECC scheme have error correction capabilities of different levels.

Memory system and memory device

According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.

Controller and memory system

A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.

A memory system according to the present embodiment includes a memory controller including a first data bus and a first address bus. A memory part includes a second data bus and a second address bus. A bridge part is capable of receiving an address from the memory controller via the first data bus, and outputs the address via the first address bus to the memory part.

Memory system with a bridge part provided between a memory and a controller

According to one embodiment, an encoder generates a write data parity from write data to memory elements. A decoder corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix. An inverter maintains or inverts all bits of a received input. Calculation by the decoder using the read data, the read data parity, and the check matrix produces a first result when an error is not included in the read data, a second result when an error is included in the read data, a third result when an error is not included in the read data and all bits of the read data are inverted, and a fourth result when an error is included in the read data and all bits of the read data are not inverted.

Memory device

An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation state (normal operation state) until no-access period which lasts from last access to next access reaches a first period. An operation control section controls operation of the access object circuit according to the output of the access detection section.

Semiconductor device and memory control method

The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

Memory system and method that changes voltage and frequency

A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

Semiconductor memory, operating method of semiconductor memory, memory controller, and system

A refresh operation at a memory cell array for keeping data stored in memory cells is enabled to be switched whether to be executed based on an external refresh request inputted from external or an internal refresh request generated internally by a refresh control unit, and therefore, when the refresh operation is executed based on the external refresh request, it becomes possible to execute an access operation for the memory cell array in accordance with an access request from external only with a necessary time for executing the operation in accordance with the access request without including a necessary time for executing the refresh operation.

Growing community of inventors

Kawasaki Kanagawa, Japan

Yasuyuki Eguchi