Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Yasuyuki Doi

Shiro Dosho

Yusuke Tokunaga

Shiro Sakiyama

Tetsuro Oomori

Kurumi Nakayama

Makoto Hattori

Yoshito Date

Kazuya Matsumoto

Kazuyoshi Nishi

Tetsuro Ohmori

Hideki Ikeda

Toru Iwata

Takashi Hirata

Tomokazu Kojima

Takahito Kushima

Tooru Suyama

Kazuhiko Nagaoka

Tsutomu Sakakibara

Hirofumi Nakagawa

Miki Fujino

Tsukasa Kawahara

Masahiro Akabori

Kenji Miyake

Shinji Miyamoto

Yoshiyuki Konishi

Kaori Nishikawa

Hideki Yoshii

A display device in which gradation wiring lines of positive polarity included in a (m)th group of wiring lines of positive polarity and gradation wiring lines of positive polarity included in a (m+1)th group of wiring lines of positive polarity are alternately provided, and in which gradation wiring lines of negative polarity included in a (m')th group of wiring lines of negative polarity and gradation wiring lines of negative polarity included in a (m&#x2032;+1)th group of wiring lines of negative polarity are alternately provided. The device further includes (n)th resistance dividing circuits of positive polarity which include (m)th resistance dividing circuits connected to the (m)th group of wiring lines of positive polarity, and (m+1)th resistance dividing circuits connected to the (m+1)th group of wiring lines of positive polarity. Resistance dividing circuits of negative polarity are connected in a similar manner to the gradation wiring lines of negative polarity.

Semiconductor integrated circuit for driving display panel, display panel driving module, and display device

A data signal loading circuit (i) which includes: a comparator CMPreceiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLPwhich is in phase with clock signal CKP, and clock signal CLNhaving a reverse phase of clock signal CKP; a comparator CMPhaving a non-inverting input terminal receiving clock signal CLP, and an inverting input terminal receiving clock signal CLN; and a comparator CMPhaving an inverting input terminal receiving clock signal CLP, and a non-inverting input terminal receiving clock signal CLN, and (ii) which, by using output signals CLand CLof the comparator CMPand the comparator CMPas clock signals for latch circuits Land L, equalizes delay times for the rise or fall of clock signals CLand CLinputted to the latch circuits Land L, and (iii) has low power consumption.

Data signal loading circuit, display panel driving circuit, and image display apparatus

A selection section () selects a step voltage, among a plurality of step voltages (SV, SV, SV, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV, SV, SV, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section () amplifies the step voltage selected by the selection section (). An output section () outputs the step voltage amplified by the amplifier section () as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Digital/analog converter circuit

A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Delay locked loop circuit

A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.

Digital-to-analog converter

In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKPand CLKNis input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

Display element drive apparatus and image display apparatus

A source driverA arranged on a liquid crystal panel includes therein in-chip reference voltage wiresextending from one end to the other end of an LSI chip. The source driverA includes therein: branch reference voltage wiresbranching off from in-chip reference voltage wires; reference voltage production buffers; a control circuitfor controlling the reference voltage production buffers; a reference voltage production resistor sectionfor subdividing the reference voltage into values of n steps; voltage level selection circuitseach for selecting one of the subdivided voltages; and output buffers. Since the reference voltages are supplied to each source drivervia wiring for connecting the in-chip reference voltage wiresin series with one another, the wiring structure for supplying the reference voltages can be simplified.

Display panel including a plurality of drivers having common wires each for providing reference voltage

For example, in order to convert a 6-bit digital signal into an analog signal, a reference voltage generating circuit for generating 17 reference voltages, a first switch circuit having 19 switch pairs each including a MOS transistor for two reference voltages adjacent to each other in accordance with upper four bits, a second switch circuit including a series circuit of 12 MOS transistors and for dividing the difference between the two selected reference voltages using combined ON-resistances into four so as to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower voltage of the two selected reference voltages or one of the three intermediate voltages in accordance with lower two bits, are provided.

A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

Signal transmission circuit

A compact-size driving voltage controller is provided which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.

Driving voltage controller

In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system () is realized.

Data transmission/reception system

Liquid crystal driving circuit, semiconductor integrated circuit device, reference voltage buffering circuit, and method for controlling the same

It is an object of the present invention to provide a high slew rate differential amplifier circuit that can reduce current consumption while maintaining stability. A P-type MOS sub-current source ( ) having a current source circuit including a transistor (M ) having a gate voltage of a P-type MOS output transistor (M ) input to a gate thereof and a constant current source transistor (M ) connected in series with the transistor (M ), the current source circuit being connected in parallel with a constant current source transistor (M ) of a P-type MOS differential input section ( ) is combined with an N-type MOS sub-current source ( ) including a current source circuit including a transistor (M ) having a gate voltage of an N-type MOS output transistor (M ) input to a gate thereof and a constant current source transistor (M ) connected in series with the transistor (M ), the current source circuit being connected in parallel with a constant current source transistor (M ) of an N-type MOS differential input section ( ). To increase a current through the differential input section when a high slew rate is required, the current source circuit including the transistor having the gate voltage of the output transistor input to the gate thereof and the constant current source transistor connected in series with the first transistor is used as a sub-current source for a differential circuit, in order to reduce a steady-state current.

Growing community of inventors

Kyoto, Japan

Yasuyuki Doi