Kyocera Corporation

Yasuyoshi Kunimatsu

Masahiko Higashi

Noriaki Hamada

Kouichi Yamaguchi

Hideto Yonekura

Yasuhide Tami

Takeshi Kubota

Akifumi Sata

Akira Furuzawa

Yohji Furukubo

A semiconductor device which includes a ceramic package main body, a semiconductor element and a closure for sealing the semiconductor element in the package. A capacitor is formed on an upper or lower surface of the closure. The capacitor has a dielectric film interposed between a pair of electrode films. The dielectric film includes a ceramic filler and an amorphous glass. The closure and the package main body are sealed. A terminal formed in the package main body and the electrode film of the capacitor are connected electrically. High-density packaging on a substrate can be achieved. High strength of the closure itself can be maintained. Thermal stress developed in the closure itself, or the conjugated portion between the closure and the package main body, can be suppressed. Reliability of a sealed structure in the semiconductor device for a long period of time can be increased.

Semiconductor device having a capacitor formed on a surface of a closure

A semiconductor device having a semiconductor element mounted on an insulating substrate and a decoupling capacitor provided on the semiconductor element. The semiconductor device minimizes the occurrence of switching noise. The semiconductor device comprises an insulating substrate, a semiconductor element mounted on said insulating substrate, and a decoupling capacitor which is joined to the upper surface of said semiconductor element and is electrically connected to said semiconductor element, wherein said decoupling capacitor has a coefficient of thermal expansion close to the coefficient of thermal expansion of said semiconductor element, and is electrically connected to said semiconductor element by soldering and is further secured to said semiconductor element.

Semiconductor device with a decoupling capacitor mounted thereon having

In a circuit board obtained by providing a metallized layer of wiring on the surface or interior of an insulation substrate, the insulation substrate is, for example, a multi-layer circuit board or a package for semiconductor element, the insutating substrate obtained from a sintered body having a linear expansion coefficient of 8 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. which is prepared by sintering a molded body containing 20 to 80% of a glass having a liner expansion coefficient of 6 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. and 80 to 20% of a filler having a linear expansion coefficient of at least 6 ppm/.degree. C. When the circuit board of the present invention is surface mounted on an outer electric circuit substrate such as a printed wiring board having a large linear expansion coefficient, the occurrence of stress due to a difference between the linear expansion coefficients of both is suppressed, and the circuit board and the outer electric circuit can be electrically connected accurately and firmly over a long period of time. Furthermore, a mounted structure of a circuit board having high reliability which can sufficiently dealt with the use of multiple pins due to large sizing of a semiconductor element can be realized. Furthermore, simultaneous sintering with the Cu metallized layer can be performed, and since the binder can be removed efficiently, the product is of high quality and is cheap.

Circuit board

Growing community of inventors

Kokubu, Japan

Yasuyoshi Kunimatsu