Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Renesas Technology Corp.

Yasuyoshi Itoh

Katsuyuki Horita

Katsuomi Shiozawa

Takashi Kuroi

Kaoru Motonami

Toru Takeguchi

Yasuo Inoue

Takaaki Murakami

Masami Hayashi

Yuichi Masutani

Shigeru Shiratake

Yuichi Yokoyama

Hiroshi Matsuo

Kenji Yasumura

Satoshi Hamamoto

Syuichi Ueno

Ritsuko Gotoda

Kenji Morisawa

Hidekazu Oda

Takeshi Kubota

Natsuo Ajika

Shingo Nagano

Kenichi Miyamoto

Masaru Aoki

Haruo Furuta

Toshio Araki

Shuuichi Ueno

Shinichi Yano

Eiji Shibata

Atsunori Nishiura

Osamu Miyagawa

Katsuomi Siozawa

A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.

Thin film transistor array substrate and liquid crystal display apparatus comprising a transparent conductive film pattern having a first type pattern and a second type pattern

In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFTis formed. Further, a dummy back channel region, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFTregion.

Method of manufacturing TFT substrate and TFT substrate

A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a mask, transforming the resist pattern using an organic solvent or a RELACS agent to cover an edge face of the etched second thin film and etching the metal film while the edge face of the second thin film is covered with the resist pattern.

Method of manufacturing multilayer thin film pattern and display device

In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 &#x3bc;m or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

Thin film transistor substrate with divided gate electrode

A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

Method of manufacturing thin film transistor array substrate and display device

An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.

Thin film transistor having an island like semiconductor layer on an insulator

An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.

Array substrate for an image display device

A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.

Thin film transistor substrate and method for manufacturing the same

A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Semiconductor device

Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

Method of manufacturing thin film transistor

A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.

Semiconductor device with a metal insulator semiconductor transistor

A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure ( ) formed on a main surface of a semiconductor substrate ( ). A pair of extensions ( ) and source/drain regions ( ) are selectively formed in the main surface so as to face each other through a channel region ( ), a silicon oxide film ( ) is formed on the trench-type element isolation structure ( ) and on the source/drain regions ( ) through a silicon oxide film ( ), sidewalls ( ) are formed on sides of the silicon oxide film ( ), a gate insulating film ( ) is formed on the main surface in a part where the channel region ( ) is formed and a gate electrode ( ) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls ( ) and the upper surface of the gate insulating film ( ).

Semiconductor device including inversely tapered gate electrode and manufacturing method thereof

Two source/drain regions ( ) belonging to separate elements which are adjacent to each other are connected through a metal layer ( ) having the same height as a height of a metal layer ( ) forming a part of a gate electrode. In a manufacturing process, an insulating layer ( ) is made of other material than and inserted between two insulating layers ( ) and ( ). The two insulating layers ( ) and ( )function as molds for burying the metal layers ( ), ( ) and ( ) therein and made of the same material. The metal layer ( ) can therefore be formed at the same height as the height of the metal layer ( ). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer

A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.

Semiconductor device manufacturing method and semiconductor device

A semiconductor device includes a silicon substrate ( ), a pair of isolating insulation films ( ), a channel region ( ), a pair of source/drain regions ( ), a pair of silicon oxide films ( ) formed on an upper surface of the silicon substrate ( ) so as to overlie the source/drain regions ( ), and a gate structure ( ) formed in a first recess defined by the upper surface of the silicon substrate ( ) over the channel region ( ) and side surfaces of the pair of silicon oxide films ( ). The gate structure ( ) includes a gate oxide film ( ) formed on the upper surface of the silicon substrate ( ), a pair of silicon oxide films ( ) formed on lower part of the side surfaces of the pair of silicon oxide films ( ), and a metal film ( ) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films ( ), the silicon oxide films ( ) and the gate oxide film ( ). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.

Growing community of inventors

Tokyo, Japan

Yasuyoshi Itoh