Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Engineering Co., Ltd.

Hitachi Information & Control Solutions, Ltd.

Hitachi Information Control Systems, Inc.

Yasuwo Watanabe

Yasuhiro Nakatsuka

Hiroshi Arita

Kenji Furuhashi

Yoshihiro Tanaka

Tomoaki Aoki

Masanobu Tanaka

Kei Ouchi

Toshinobu Kanai

Kotaro Shimamura

A transmit packet generated by a CPUis held in a buffer(). From among packets received from Ethernet(), a packet, a destination of which is a communication device, is held in the buffer(). A packet which should be transmitted is transmitted from a transfer judging circuitto Ethernetorthrough a MAC unitor. If a transfer judging circuitjudges a packet from the Ethernetto be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernetthrough MAC. If a usage rate of a transferring FIFO buffer() exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer() on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernetorin preference to the transmit packet. This prevents a transfer buffer means from overflowing.

Packet communication device, packet communication system, packet communication module, data processor, and data transfer system

Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system

A packet communication apparatus capable of performing packet conversion at high speed for packet transfer or packet transmission/reception has: a packet conversion unit for performing packet conversion for a reception packet received at a plurality of communication units and for a transmission packet to be transmitted from the plurality of communication units; and a transfer control unit for outputting, when the reception packet received by the communication unit is judged as a the transfer packet, the reception packet to a transfer buffer, for outputting the transmission packet to the communication unit corresponding to the communication object at a destination of the transmission packet generated by a packet generating and processing unit, and for outputting the transfer packet to the communication unit corresponding to the communication object at a destination of the transfer packet stored in the transfer buffer.

Packet communication apparatus

A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

Growing community of inventors

Hitachiohta, Japan

Yasuwo Watanabe