Taiwan Semiconductor Manufacturing Comp. Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Other

Applied Materials, Inc.

Matsushita Electronics Corporation

Yasutoshi Okuno

Sung-Li Wang

Pang-Yen Tsai

Mrunal Abhijith Khaderbad

Clement Hsingjen Wann

Meng-Hsuan Hsiao

Peng-Wei Chu

Teng-Chun Tsai

Ziwei Fang

Andrew Joseph Kelly

Winnie Victoria Wei-Ning Chen

Akihiko Tsuzumitani

Liang-Gi Yao

Yoshihiro Mori

Hidehiro Fujiwara

Tung-Ying Lee

Hsien-Yu Pan

I-Ming Chang

Yu-Ming Lin

Yen-Huei Chen

Hung-Jen Liao

Ling-Yen Yeh

Cheng-Yi Peng

Chih-Yu Lin

Yusuke Oniki

Michikazu Matsumoto

Akira Mineji

Tetsu Ohtou

Pei-Wei Lee

Cheng-Long Chen

Kuan-Lun Cheng

Ching-Wei Tsai

Tung Ying Lee

Chih-Hao Chang

Yi-Tang Lin

Chi-Yuan Shih

Chien-Chang Su

Fu-Ting Yen

Jiun-Jia Huang

Shih-Chuan Chiu

Wang-Chun Huang

Shou Zen Chang

Wei-Chun Tsai

Pei-Shan Chien

Wei-Hsiung Tseng

Yuan-Fu Shao

Yee-Chia Yeo

Chih-Hsin Ko

Marcus Johannes Henricus Van Dal

Blandine Duriez

Shen-Nan Lee

Ding-Kang Shih

Kuan-Ting Liu

Kun-Yu Lee

Ta-Chun Ma

Tsung-Yu Hung

Masaru Yamada

Yen-Ming Chen

Keng-Chu Lin

Hiroshi Iwai

Chung-Cheng Wu

Martin Christopher Holland

Yu-Yun Peng

Hisashi Ogawa

Shuen-Shin Liang

Young Seen Lee

Takashi Nakabayashi

Yi-Fang Pai

Masafumi Kubota

Meng-Chun Chang

Hemant P Mungekar

Hideyuki Arai

Manoj Vellaikal

Gwan-Sin Chang

Wei-Shan Hu

Hiroshi Yuasa

Yoshikazu Tsunemine

Lars-Ake Ragnarsson

Tom Schram

Naohisa Sengoku

Toshihiko Nagai

Joshua Tseng

Kuniyuki Kakushima

Stefan Kubicek

Che-Yu Yeh

Tetsuya Matsutani

Sung-li Wang

Kazuo Tsutsui

Thomas Y Hoffman

Katsuyoshi Joukyu

Seiji Ueda

Ying-Hsuan Wang

A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

Memory array circuit and method of manufacturing same

A semiconductor structure includes a substrate, a first silicide, and a second silicide. The substrate has a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type. The first silicide is on the first epitaxy region, the first silicide comprising a first metal and a second metal, and the second silicide is on the second epitaxy region. A work function of the first silicide is greater than a work function of the second silicide.

Semiconductor structure and method for manufacturing the same

A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.

Selective dual silicide formation

A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Selective dual silicide formation using a maskless fabrication process flow

A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

Semiconductor device with source/drain contact formed using bottom-up deposition

A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.

Channel mobility improvement

A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Interface profile control in epitaxial structures for semiconductor devices

A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

Contact structures with deposited silicide layers

A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

A device includes a semiconductive fin, an isolation structure, a gate structure, dielectric spacers, and source/drain epitaxial structures. The isolation structure surrounds a bottom portion of the semiconductive fin. The gate structure is over the semiconductive fin. The dielectric spacers are on opposite sides of the semiconductive fin and over the isolation structure. The dielectric spacers include nitride. The source/drain epitaxial structures are on opposite sides of the gate structure and over the dielectric spacers. The source/drain epitaxial structures have hexagon shapes.

Semiconductor device having spacer residue

A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

Semiconductor device and manufacturing method thereof

In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor material.

Semiconductor device and method

The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

Field effect transistors with dual silicide contact structures

A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.

Conductive structure formed by cyclic chemical vapor deposition

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Hsinchu, Taiwan

Yasutoshi Okuno