Mitsubishi Denki Kabushiki Kaisha

Yasutomo Kajikawa

Hirotaka Kizuki

Motoharu Miyashita

Yutaka Mihashi

Shoichi Karakida

Yutaka Nagai

Yasuaki Yoshida

Akihiro Shima

Zempei Kawazu

Yuji Ohkura

An undoped GaAs layer is formed on a GaAs substrate. Thallium is adhered to the undoped GaAs layer to a thickness of at least one atomic layer. After adhesion of thallium, GaInNAs is epitaxially grown on the undoped GaAs layer by chemical vapor deposition.

Method of forming a GaInNAs layer

A semiconductor laser device on a GaAs substrate and having an oscillation wavelength of 1.3 &mgr;m or 1.55 &mgr;m and a method of producing the laser device. The laser device has a BTlGaAs active layer that lattice matches with the GaAs substrate. To grow the BTlGaAs active layer, organometallic vapor phase deposition is employed with cyclopentadienyl thallium as the source of Tl.

Semiconductor laser device and method of producing the same

A semiconductor device includes a GaAs substrate having a lattice constant; and a III-V mixed crystal semiconductor layer disposed on the GaAs substrate, containing Tl (thallium) and Ga (gallium) as Group III elements and As (arsenic) as a Group V element, and having a lattice constant larger than the lattice constant of the GaAs substrate. Therefore, the lattice mismatch of the III-V mixed crystal semiconductor layer with GaAs and the band gap energy of the III-V mixed crystal semiconductor layer are smaller than those of an InGaAs layer, resulting in a semiconductor device with improved operating characteristics and reliability.

Semiconductor device including T1 GaAs layer

A method of fabricating a semiconductor laser device includes successively forming an active layer and upper cladding layers on a lower cladding layer, etching and removing portions except regions of the upper cladding layers where a current is to flow to form a stripe-shaped ridge structure, and forming a buffer layer comprising Al.sub.x Ga.sub.1-x As having an Al composition ratio x of 0 to 0.3 on a surface of the upper cladding layers exposed by the etching and forming a current blocking layer of first conductivity type Al.sub.y Ga.sub.1-y As having an Al composition ratio y of at least 0.5 on the buffer layer to bury portions of the upper cladding layers which are not removed by the etching process. Therefore, since the layer grown on the upper cladding layer exposed by etching of AlGaAs or GaAs having a low Al composition ratio (0-0.3), three-dimensional growth of and crystalline defects in the buffer layer are suppressed. Current leakage is suppressed, so that a semiconductor laser device having a low threshold current and a high efficiency is fabricated with a stable yield.

Semiconductor laser device and method of fabricating semiconductor laser

A method of growing a compound semiconductor layer includes epitaxially growing a III-V compound semiconductor layer including nitrogen (N) for as the Group V element on a front surface of a semiconductor substrate of cadmium telluride (CdTe). Therefore, the atoms of the crystal lattice of the III-V compound semiconductor layer are periodically lattice-matched with the atoms of the crystal lattice of the CdTe semiconductor substrate, whereby the III-V compound semiconductor layer is epitaxially grown with high crystalline quality.

Method of growing compound semiconductor layer

A semiconductor device includes a semiconductor substrate, a strained multi-quantum well with alternatingly laminated first barrier layers and well layers with second barrier layers as outermost layers of the strained MQW structure. The strained MQW structure has a safety factor K.sub.safe =3.9; and ##EQU1## Therefore, it is possible to make the strained MQW structure have a sufficient margin with respect to critical conditions concerning the generation of dislocations, and deterioration of operational characteristics in continuous operation of the semiconductor device can be suppressed so that the reliability of the semiconductor device is enhanced.

Semiconductor device and fabricating method thereof

In the inventive heterojunction bipolar transistor and method of manufacturing the same, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed, and thereafter an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of an external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-alignment manner through the opening of the insulation film. Thus, transistor performance is improved and a precision element size is able to be obtained.

Heterojunction bipolar transistor

A method of manufacturing a heterojunction bipolar transistor comprising the sequential steps of; forming an extra epitaxial layer (9) on a layered structure which consists of a collector layer (2), a base layer (3), and an emitter layer (4) provided on a semiconductor substrate (1) in that order; forming a recess (10) by selectively etching the extra epitaxial layer (9); and forming an emitter electrode (70a) and a resist mask (70a) in the recess (10) by way of self alignment scheme, where the resist mask (70a) covers the emitter electrode (60e). An extremely small-sized resist mask (70a) can be formed, and extremely small-sized emitter mesa (4a) is formed by applying wet etching to the epitaxial layer (9) and the emitter layer (4) using the resist mask (70a).

Method of manufacturing semiconductor device

A heterojunction bipolar transistor and method of manufacturing the same is disclosed in which, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed. Subsequently an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of the external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-aligned manner through the opening of the insulation film. Thus, transistor performance is improved and element size accuracy is improved.

Growing community of inventors

Tokyo, Japan

Yasutomo Kajikawa