Renesas Electronics Corporation

Renesas Technology Corp.

Other

Yasuto Igarashi

Yoshihiko Yasu

Kazumasa Yanagisawa

Toshio Sasaki

Naozumi Morino

Takayuki Sasaki

Ryo Mori

Kazuki Fukuoka

Takashi Kuraishi

Koichiro Ishibashi

Yuji Tanaka

Takahiro Irita

Sadayuki Morita

Yuri Azuma

Masafumi Onouchi

Kazuo Otsuga

Yasunobu Aoki

Mariko Ohtsuka

Kentaro Yamawaki

Toshiaki Takahira

A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Semiconductor integrated circuit

Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

Semiconductor integrated circuit device

A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Semiconductor device

A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.

The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.

The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Semiconductor integrated circuit with power-on state stabilization

A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

Semiconductor integrated circuit device having an improved operation control for a dynamic memory

Growing community of inventors

Tokyo, Japan

Yasuto Igarashi