Mitsubishi Denki Kabushiki Kaisha

Yasutaka Kohno

Tomoki Oku

Masayuki Sakai

Ryo Hattori

A high power output semiconductor device having a plurality of FET elements on a semi-insulating semiconductor substrate including a first conductivity type semiconductor layer on the semi-insulating semiconductor substrate, a plurality of source and drain electrodes alternatingly arranged on the semiconductor layer, a plurality of gate electrodes respectively disposed in gate recesses formed by etching respective surface regions of the semiconductor layer between each adjacent source and drain electrodes. The gate recess has a asymmetrical two-stage recess structure having a second bottom surface only at the source side of the recess at a depth between a first bottom surface in contact with the gate electrode and the upper surface of the semiconductor layer and is not in contact with the gate electrode. Therefore, the thickness of the active layer at the source side is increased as compared with that in the one-stage recess structure, with the result that the source resistance is reduced because of an increase in the thickness of the active layer at the source side region while avoiding deterioration of the gate drain breakdown voltage due to an increase in the thickness of the active layer at the drain side region.

Recessed gate field effect transistor

A method for producing a refractory metal gate electrode includes forming a patterning mask layer that is dissolved in a solution including hydrogen ions and having an aperture on a semiconductor substrate; forming a gate metal layer having an ionization potential larger than hydrogen on the entire surface of the patterning mask layer; forming a low resistance metal layer of a predetermined configuration having an ionization potential smaller than hydrogen on the gate metal layer; covering at least an upper surface of the low resistance metal layer with a film that has no reductive reaction with a solution including hydrogen ions; and removing the patterning mask layer using a solution including hydrogen ions after patterning the gate metal layer. An electrolytic reaction of a system including the gate metal layer, the low resistance metal layer, and the solution including hydrogen ions is suppressed by a film covering at least an upper surface of the low resistance metal layer, and localized abnormal dissolution of the gate metal when removing the patterning mask layer using the solution including the hydrogen ions is suppressed.

Method for producing refractory metal gate electrode

In a field effect transistor including a Schottky gate electrode disposed on an active region in a compound semiconductor substrate, a compressive stress of the gate electrode and a tensile stress of an insulating film serving as a passivation are concentrated on the lower edges of the gate electrode, whereby positive piezoelectric charges are produced in the compound semiconductor substrate in the vicinity of the gate electrode. The positive piezoelectric charges increase the effective donor concentration, reducing the thickness of the surface depletion layer. As the result, channel narrowing due to the surface depletion layer is suppressed.

Field effect transistor and method for producing the field effect

In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the stress in the gate metal and the stress produced by the insulating film on the gate electrode cancel so that threshold voltage is not a function of gate orientation relative to the crystalline directions of the substrate.

Semiconductor device with reduced stress applied to gate electrode

A compound semiconductor device includes a plurality of epitaxial compound semiconductor layers including an InGaAs layer as the uppermost layer disposed on a semi-insulating compound semiconductor substrate, a groove penetrating through at least the InGaAs layer, an insulating film disposed on the side surfaces of the groove and having ends extending beyond the groove, a gate electrode disposed in the groove and on the insulating film, and source and drain electrodes on the InGaAs layer at opposite sides of the groove self-aligned with the ends of the insulating film.

Compound semiconductor device with a particular gate structure

A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited. Therefore, the space between the over-hanging portion of the T-shaped gate electrode and the source electrode increases and the gate-to-source capacitance is reduced.

Method of manufacturing a field effect transistor with a T-shaped gate

In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the vector sum of the stress in the gate metal and the stress produced by the insulating film on the gate electrode is zero. A production method of a semiconductor device includes producing a gate electrode having the same but opposite stress of an insulating film by sputtering under an adjusted gas pressure a target of WSi.sub.x and depositing an insulating film covering the gate electrode.

Semiconductor device with reduced stress on gate electrode

A method of producing a semiconductor device including the steps of depositing a refractory metal gate electrode at a predetermined region of a semi-insulating substrate surface, and thereafter depositing an insulating film at regions other than the gate electrode region, wherein the production of the insulating film is carried out by an electron cyclotron resonance plasma CVD method while applying a high frequency electrical bias to the substrate.

Method of producing a semiconductor device using electron cyclotron

A method for producing a field effect transistor includes depositing an insulating film on an active layer produced in a semiconductor substrate and removing a part of the insulating film, leaving a side wall substantially perpendicular to the substrate. A refractory metal is deposited on the surface of the semiconductor substrate and the insulating film. The refractory metal is removed except for a portion at the side wall of the insulating film to produce a gate electrode. A high dopant concentration region is ion implanted using the insulating film and refractory metal as a mask. The insulating film is removed and an intermediate dopant concentration region is ion implanted using the refractory metal as a mask. A source electrode is produced on the high dopant concentration region and a drain electrode is produced on the intermediate dopant concentration region. The invention may be used to produce asymmetrically doped drain and gate regions and an asymmetrically disposed gate electrode.

Production method of a semiconductor device

A method for producing a field effect transistor includes depositing an insulating film on an active layer produced in a semiconductor substrate and removing a part of the insulating film, leaving a side wall substantially perpendicular to the substrate. A refractory metal is deposited on the surface of the semiconductor substrate and the insulating film. The refractory metal is removed except for a portion at the side wall of the insulating film to produce a gate electrode. A high dopant concentration region is ion implanted using the insulating film and refractory metal as a mask. The insulating film is removed and an intermediate dopant concentration region is ion implanted using the refractory metal as a mask. A source electrode is produced on the high dopant cocentration region and a drain electrode is produced on the intermediate dopant concentration region. The invention may be used to produce asymmetrically doped drain and gate regions and an asymmetrically disposed gate electrode.

Method for producing a semiconductor device

A semiconductor device, such as a MESFET having a self-aligned gate, and a method for production thereof. A triple layer film is formed on the semiconductor substrate, then anisotropically etched to produce a gate structure which is used as a mask in an ion implantation step for forming a source and drain. The triple layer film includes a lower high melting point metal silicide, an upper similar metal silicide and an intermediate high melting point metal layer. The first layer forms a Schottky barrier with the semiconductor substrate and serves as a metal silicide gate. The upper layer serves as a dummy gate. The intermediate metal layer serves to protect the metal silicide layers during the etching step, serves as an etchant stop during removal of the dummy gate, and also serves to protect the Schottky barrier after the device is completed. After removal of the dummy gate, a low resistance metal such as gold is self-alignedly deposited in its place and serves to improve the high frequency performance of the device.

Semiconductor device and method for manufacture thereof

A field effect transistor includes a high concentration doping layer self-alignedly produced using a refractory metal silicide gate as a mask for ion implantation in a semi-insulating substrate. The distance between the refractory metal gate and the high concentration doping layer which becomes a source region is shorter than the distance between the refractory metal gate and a high concentration doping layer which becomes a drain region. A method of producing a field effect transistor having an offset refractory metal silicide gate includes depositing a refractory metal silicide layer, a refractory metal film, and a first insulator film successively on an active layer which is produced on a semi-insulating substate. The deposited layers are patterned with a resist film for producing a gate pattern mask for etching the respective layers all at once or one-by-one. High dopant concentration source and drain regions are formed by ion implantation and annealing. A second insulator film is deposited on the entire surface of the substrate. The structure is etched to leave the second insulator film only at one side of the gate using reactive ion etching oblique to the substrate. Alternatively, the second insulator film is deposited to cover only one of the sides of the gate on the substrate. Etching is carried out at only one side of the refractory metal silicide film using the first and second insulator films as masks. Source and drain electrodes are formed after removing the first and second insulator films.

Method of making asymmetrical gate field effect transistor

A method of producing a semiconductor device, such as a MESFET having a self-aligned gate. A triple layer film is formed on the semiconductor substrate. The lowermost layer is a high melting point metal silicide, the intermediate layer a thin high melting point metal and the upper layer an insulator. The thicknesses and etching rates of the layers are selected such that the thin intermediate metal layer protects the underlying silicide and overlying insulator layers during etching. The three layers are anisotropically etched to produce a well-formed gate structure which is used as a mask in an ion implantation step for forming source and drain regions. A subsequent selective etching process removes the insulator layer (which serves as a dummy gate) exposing the underlying silicide layer on which is deposited a low resistance metal such as gold in a self-aligned fashion thereby to improve the high frequency performance of the device.

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Itami, Japan

Yasutaka Kohno