Hitachi, Ltd.

Yasushiro Nishioka

Kiichiro Mukai

Noriyuki Sakuma

Hiroshi Shinriki

Iwao Takemoto

Takeo Shiba

Shinichiro Kimura

Makoto Ohkura

Keiichi Higeta

Katsumi Ogiue

Masanobu Miyao

Noriyuki Homma

Ryo Haruta

Kunihiko Yamaguchi

Akihisa Uchida

Terunori Warabisako

Takashi Tokuyama

Ichiro Mitamura

A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.

Process for producing a semiconductor device

Semiconductor capacitor device with dual dielectric

A reaction-preventing film is provided between a capacitor insulating film made of a material having a high dielectric constant, such as Ta.sub.2 O.sub.5, and an upper electrode in order to prevent a reaction of the upper electrode with the capacitor insulating film. This effectively prevents the reaction between the upper electrode and the capacitor caused by a heat treatment conducted after formation of the capacitor, and hence prevents an increase in leakage current caused by the reaction. Thus, the reliability of a semiconductor device is remarkably increased.

Semiconductor device

A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

Semiconductor memory device

A semiconductor device comprising a first electrode, a dielectric film and a second electrode which are stacked and formed on a semiconductor layer with the second electrode in contact with the semiconductor layer. A diode is formed of the second electrode and the semiconductor layer, and a capacitor is formed of the first electrode, the dielectric film and the second electrode.

At least one layer of insulator film and single-crystal film are alternately stacked and deposited on a surface of a semiconductor substrate, and an impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor. Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.

Three-dimensional semiconductor device with thin film monocrystalline

Growing community of inventors

Tokyo, Japan

Yasushiro Nishioka