Fujitsu Corporation

Yasushi Umezawa

Takeshi Shimizu

Wolf-Dietrich Weber

Patrick James Helland

Patrick N Conway

Takashi Miyoshi

Kazunori Masuyama

Sudheer Miryala

Jeremy J Farrell

Hitoshi Oi

Wing Leong Poon

A data transfer apparatus includes a plurality of input ports, a plurality of output ports and a switch unit between the plurality of input ports and the plurality of output ports. Each input port includes an input buffer configured to store input data including destination information indicating destinations of respective pieces of the input data, a first buffer monitoring unit configured to monitor a first usage rate of the input buffer, and a first frequency control unit configured to control a first operating frequency of the input buffer on the basis of the first usage rate. Each output port includes an output buffer configured to store output data, a second buffer monitoring unit configured to monitor a second usage rate of the output buffer, and a second frequency control unit configured to control a second operating frequency of the output buffer on the basis of the second usage rate.

Data transfer apparatus and data transfer method

A relay device includes: memories, each memory being operable to store at least a data pair formed of a MAC address and a port number; a search unit to search only amongst ones of the memories having valid data pairs when searching for a port number based upon a MAC address; a data moving unit to move valid data pairs to different locations within the plurality of memories in order to reduce a total number of memories, amongst the plurality thereof, having valid data pairs; and a power supply controller to selectively stop supplying power to ones of the memories storing only invalid data.

Relay device, MAC address search method

An apparatus includes a switching unit to output data input from an input unit to an output unit to which the data is to be output, and an input control unit, wherein input units included in a same group among a plurality of input units each have a buffer to store data received from another apparatus; a multiplexer connected to the buffer and to a buffer in another input unit in the same group, and capable of selectively outputting data; and an input data processing portion connected to the multiplexer and performing specific input data processing on data input from the multiplexer and outputting data after the specific input data processing to the switching unit, wherein the input control unit controls a data output selection of the multiplexer and controls supply of power or supply of a clock signal to the multiplexer and the input data processing portion.

Network apparatus

A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information of configuration of the memory circuit with error protection circuit from the design information; and a circuit arrangement controller for determining whether to insert a check circuit for supplying a check signal into the memory circuit to verify the error protection circuit on the configuration information.

Circuit design apparatus and circuit design method

A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

Fault containment and error handling in a partitioned system with shared resources

A computer architecture for avoiding a deadlock condition in an interconnection network comprises a messaging buffer having a size pre-calculated to temporarily store outgoing messages from a node. Messages are classified according to their service requirements and messaging protocols, and reserved quotas in the messaging buffer are allocated for different types of messages. The allocations of the reserved quotas are controlled by a mechanism that, to prevent overflow, limits the maximum number of messages that can be outstanding at any time. The messaging buffer is sized large enough to guarantee that a node is always able to service incoming messages, thereby avoiding deadlock and facilitating forward progress in communications. The buffer may be bypassed to improve system performance when the buffer is empty or when data in the buffer is corrupted. In addition, a multicast engine facilitates dense packing of the buffer and derives information from a message header to determine whether there is a multicast to perform and to permit passage of messages. Other considerations to reduce the buffer size are incorporated.

Growing community of inventors

Kawasaki, Japan

Yasushi Umezawa