Mitsubishi Electric Corporation

Yasushi Takaki

Kosuke Miyazaki

Yoichiro Tarui

Shiro Hino

Yoshinori Matsuno

Kinya Yamashita

Kensuke Taguchi

Masaki Ueno

Kohei Ebihara

Eisuke Suekawa

Takaaki Tominaga

Chihiro Tadokoro

According to the present disclosure, a semiconductor manufacturing apparatus comprises a pickup stage having a mechanism for lifting and lowering a semiconductor chip having a square shape. The pickup stage comprises first pushing-up blocks at four corners. Each of the first pushing-up blocks comprises a first side parallel to one side of the semiconductor chip, a second side parallel to another side of the semiconductor chip, and an offset portion formed between the first side and the second side to be offset to an inward side of an intersection point of respective extension lines of the first side and the second side.

Semiconductor manufacturing apparatus

A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.

Method for manufacturing semiconductor device

The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.

Semiconductor device and power conversion device

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

Semiconductor test apparatus and semiconductor test method

A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.

Semiconductor device and method for manufacturing semiconductor device

Polysilicon films (P,P) are simultaneously formed on a wafer (W) and a monitor wafer (W) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P) formed on the monitor wafer (W) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P) formed on the wafer (W) is etched using the selected mask pattern to form the polysilicon resistor ().

Manufacturing method for a semiconductor device including a polysilicon resistor

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having an n-type drift layer, and a p-type well region formed in a surface portion of a part of the drift layer, an insulating film provided on the well region, a gate built-in resistor formed of polysilicon in contact with a surface of the insulating film, an interlayer insulating film formed on the gate built-in resistor, a gate contact wire that is connected to a gate pad and formed on the interlayer insulating film, a gate wire provided on the interlayer insulating layer so as to be apart from the gate contact wire, a first gate contact for electrically connecting the gate contact wire and the gate built-in resistor, and a second gate contact for electrically connecting the gate wire and the gate built-in resistor.

Silicon carbide semiconductor device

The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region.

Growing community of inventors

Tokyo, Japan

Yasushi Takaki