Sharp Kabushiki Kaisha Corporation

Toray Opelontex Co., Ltd.

Yasushi Sasaki

Yuhichiroh Murakami

Shige Furuta

Shuji Nishi

Seijirou Gyouten

Makoto Yokoyama

Etsuo Yamamoto

Takahiro Yamaguchi

Shinsaku Shimizu

Hidekazu Yamanaka

Hiroyuki Ohkawa

Takuya Hachida

Sachio Tsujino

Atsushi Okada

Hiroyuki Adachi

Junichi Yamada

Satoshi Fujii

Koji Hirano

Eiji Matsuda

Osamu Sasaki

Toshihiro Tanaka

Yasushi Fujita

Kohei Hosoyachi

Takayuki Yanagawa

Fumitake Mori

A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Display device using binary driver having several holding circuits

A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Data signal line drive circuit and liquid crystal display device provided with same

Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T, T, T) whose on-off state is controlled at relatively high on-duty and a second group (T, T, T, T, T, T) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.

Shift register circuit

A unit circuitof a shift register is provided with a transistor Trfor supplying an off potential to a node nvia a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Trdoes not turn on and charge does not escape from the node. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.

Shift register

A unit circuitof a shift register is provided with a transistor Trhaving a drain terminal connected to a node N, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N. The unit circuitis further provided with a transistor Trhaving a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node Nto be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Trbefore the initialization.

The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL(i&#x2212;1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer () makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line(i&#x2212;1)+k via a correction capacitance element (Cc). The inversion delayer () makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

Data signal line drive circuit, data signal line drive method and display device

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A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal. The shift direction is switched by changing the generation order of pulses of clock signals.

A demultiplexer circuit () of a display device according to one aspect of the present invention includes signal input lines (Vn), control lines (BSW, GSW, and RSW), and sampling transistors (RG, andB). Sampling transistors connected to one signal input line includes first and second sampling transistors. A first sampling transistor (B) includes a control electrode () which branches to a first branch part () and a second branch part (), either one of an input electrode () and an output electrode () that are disposed between a first branch part () and a second branch part (), and other one of an input electrode () and an output electrode () that are disposed outside of a first branch part () and a second branch part ().

Display device

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Trswitches between whether or not to provide an output of an on-potential output unitto a gate terminal of Trin accordance with an output of a set control unit. The set control unitcontrols a gate terminal of Trinto a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr. The gate potential of Tris raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

The purpose of the present invention is to reduce a circuit size of a shift register. A shift register of the present invention includes stages each including a holding circuit () and a clock output circuit (). The clock output circuit () includes an output terminal (O) that outputs a signal having a high electric potential or a low electric potential, depending on at least one of outputs (Q) from the holding circuit () and on a second clock signal. The holding circuit () carries out a reset operation in accordance with a first clock signal supplied to a transistor (N).

Shift register, scan signal line driver circuit, display panel and display device

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

A unit circuit () includes: a transistor (T) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T) which supplies the ON voltage to a control terminal of the transistor (T) in accordance with an input signal (IN); a transistor (T) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.

Shift register including unit circuits connected in multistage manner, and display device

The purpose of the present invention is to achieve a display device capable of performing an all-selecting drive for gate bus lines without increasing the number of circuit elements more than heretofore and without lowering withstand voltage reliability. In a stage constituent circuit, which constitutes a shift register in a gate driver, an all-selecting signal (ALL-ON) for simultaneously turning all of gate bus lines to a selected state is given, as a low-potential power supply, to a source terminal of a thin film transistor (Tr) for setting, at a low level, a QB node provided for setting a scanning signal (OUT) at the low level and to a source terminal of a thin film transistor (Tr) for setting, at the low level, a Q node provided for setting the scanning signal (OUT) at a high level. A wiring (ALL-ON wiring) for supplying a low-potential power supply to the gate driver and a wiring (VSS wiring) for supplying the low-potential power supply to a circuit other than the gate driver are power supply wirings independent of each other.

A memory-type liquid crystal display device includes transistors (N, N), retention electrodes (MRY), refresh output control sections (RS), and capacitors (Cb). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Growing community of inventors

Osaka, Japan

Yasushi Sasaki