Nec Corporation

Yasushi Ooi

Masayuki Mizuno

Yutaka Yokoyama

Yoshikuni Sato

Hideo Ishida

Yoshiyuki Miki

In a video coding apparatus, coding/decoding circuitry provides motion-compensated inter-frame prediction coding on input frames by using reference frames so that the input frames are coded into an intra-frame coded picture, a predictive coded picture or a bi-directionally predictive coded picture and decoding the coded frames to produce reference frames. Decision circuitry determines the magnitude of motion of the input frames relative to the reference frames, determines the interval between successive frames of the predictive coded picture according to the determined magnitude of motion and reorders the input frames according to the determined interval.

Video coding by adaptively controlling the interval between successive predictive-coded frames according to magnitude of motion

Video images including a fade transition are encoded using inter-frame prediction. A fade detector is provided to detect a fade transition by way of analyzing incoming images successively applied thereto. The fade detector generates first information indicating if the fade transition is fade-in fade-out, and also predicts fade duration and then generates second information indicating the predicted fade duration. A bit amount adjuster is provided to adjust allocated bit amount during fade using the first and second information. A motion image encoder is provided to encode the incoming images using the number of bits which has been determined by the bit amount adjuster.

Apparatus and method for encoding video images including fade transition

In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference-picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

Motion vector estimating apparatus with high speed and method of estimating motion vector

In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

Video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 are coupled with frame memory 10 through buffer and frame memory controlling portion 9 and controlling processor 1 through host interface portion 2. Frame memory 10 is accessed by video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 in time sharing manner. Controlling of video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 is centralized in controlling processor 1. Portions in dotted frame 20 are integrated in one LSI chip.

Picture coding apparatus

A moving picture coding and decoding circuit which can cope with a plurality of algorithms to reduce the number of components and facilitate extension. A picture to be coded is inputted to a motion detection/prediction section, which outputs a predictive difference signal and a predictive signal. DCT processing and quantization are performed for the predictive difference signal by a conversion coding and decoding section, from which a conversion coefficient signal is outputted to an interface bus. The conversion coding and decoding section also executes dequantization and inverse DCT processing of the conversion coefficient, adds the predictive signal to the conversion coefficient and outputs a result of the picture coding to an image data bus. A programmable architecture as in a digital signal processor is applied to the conversion coding and decoding section. The conversion coefficient outputted from the conversion coding and decoding section is stored into a FIFO memory of a zigzag scan/entropy coding section and then undergoes coding in an entropy coding section. A bit stream thus coded is stored once into and then outputted as codes from another FIFO memory.

Moving picture coding and decoding circuit

A pipelined data processing system has an instruction set containing a stall instruction, and includes a plurality of stages and a pipeline controller for controlling execution and stall of a pipeline operation. The pipeline controller is configured to put the stages into a 'frozen' condition on the basis of a stall signal generated by execution of the stall instruction, and to return the stages from the 'frozen' condition to a 'run' condition on the basis of an output pulse generated by a timer designated by an operand part of the stall instruction.

Pipelined data processing system capable of stalling and resuming a

A data processing system for a picture coding, includes a data memory for storing a discrete cosine transform (DCT) coefficient data successively transferred one after another, a flipflop set prior to the successive transfer of the DCT coefficient data, and a non-zero detector for detecting a non-zero data when the DCT coefficient data is successively transferred. When the non-zero data is detected, the non-zero detector resets the flipflop. When the successive transfer of the DCT coefficient data has been completed, an entropy coding central processing unit (CPU) discriminates on the basis of the condition of the flipflop whether or not all of the data stored in the data memory is zero, so that if the condition of the flipflop indicates that all of the data stored in the data memory is zero, the entropy coding CPU does not read the data memory.

Data processing system for picture coding processing

An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S&lt;P and P is a positive integer); comparators which examine whether the inputted y satisfies x+log.sub.2 y.ltoreq.P for each integral number of x, and examine whether the inputted x satisfies y+log.sub.2 x.ltoreq.P for each integral number of y; an escape signal generation section which outputs an escape signal according to the output of the coincidence detectors and the comparators; an address generation section which generates and outputs an address signal from values x and y and an identification address for identifying that x and y are integers; a priority control section which inputs the output from the coincidence detectors, determines which signal is outputted with precedence and outputs it; and a multiplexer which selects and outputs an address signal in accordance with the output from the priority control section.

Address generating circuit of a two-dimensional coding table

A variable length code decoding circuit includes a decoding table storing data, which has an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding the variable bit length code per n bits (n is an integer greater than or equal to 2), an intermediate field indicative of a shifting magnitude of the shift register upon completion of decoding, and a lower field indicative of a state of code decoding. The bit sequence of the variable bit length code in a shift register is shifted in a magnitude corresponding to a shifting magnitude indicated in the intermediate field when data indicative of the code decoding state in the lower field of the data read out from the decoding table storage means indicates completion of decoding and corresponding to n bits when the data indicative of the code decoding state in the lower field indicates continuation of decoding. An address for accessing the decoding table is generated by replacing the intermediate field and the lower field with leading n bits of the shift register.

Decoding circuit for variable length code

A nesting management mechanism for use in a loop controlling system, comprises a program counter coupled to a program counter bus and incremented each time one instruction is executed, and a loop counter coupled with the program counter bus and set with the number of loops to be executed when a loop execution is executed. The loop counter is decremented each time one loop is completed. A loop start address register is coupled to the program counter bus and set with a loop start address when the loop execution is executed, and a loop end address register is coupled to the program counter bus and set with a loop end address when the loop execution is executed. First, second and third independent hardware stacks of a first-in last-out type are provided for the loop counter, the loop start address register, and the loop end address register, respectively, so as to save respective contents of the loop counter, the loop start address register, and the loop end address register at the time of a loop nesting.

Nesting management mechanism for use in loop control system

A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.

Data processor which efficiently accesses main memory and input/output

In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).

Vector processor which can be formed by an integrated circuit of a small

A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the variable word length instruction in accordance with the progress of the instruction decoding, and another adder for adding the length of the decoded instruction portions to the program counter so as to update the program counter. Further, there is provided a circuit for calculating an operand effective address by using the value of the program counter in the course of the variable word length instruction decoding. Thus, the updating of the program counter and the generation of the effective address are concurrently executed.

Program counter and indirect address calculation system which

A data processing apparatus has a plurality of execution status and is adapted to control in accordance with the respective execution conditions the allowance of the execution of an instruction requiring the reference to the internal resource. The processing apparatus also comprises a register for holding the execution status, and another register for holding information controlling the reference to the internal resource. A comparator responds to the contents of the first and second registers to output a signal indicating whether the reference is allowed or not. The output signal and a strobe signal are fed to a gate, which then controls an actual reference to the internal resource.

Growing community of inventors

Tokyo, Japan

Yasushi Ooi