Denso Corporation

Toyota Jidosha Kabushiki Kaisha

Fuji Electric Co., Ltd.

Yasushi Okura

Norihito Tokura

Akira Kuroyanagi

Hidefumi Takaya

Kenji Kouno

Seiji Noguchi

Hiromitsu Tanabe

Hiroshi Miyata

Souichi Yoshida

Kimimori Hamada

Masayuki Takenaka

Kuniaki Mamitsu

Naohiko Hirano

Kyosuke Miyagi

A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element, which has a protective film having an opening that exposes a part of a source electrode and disposed/provided to position an end portion thereof on the source electrode. A rewiring layer has wiring that is connected to the source electrode and to a conductive connecting member, and an insulator that covers a part of the source wiring. The insulator includes: an insulating film having (a) an opening for exposing a part of the source wiring, and (b) an end portion of the opening provided in a facing region of the opening; and an insulating film having (c) (i) an opening for exposing a part of the source wiring having a solder arranged therein and (ii) a connecting member arranged therein.

Semiconductor device

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.

The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

Insulated gate semiconductor device and method for producing the same

The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor deviceincludes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor devicealso has a plurality of gate trenchesin the cell area and a plurality of terminal trenchesin the terminal area. The gate trenchesare formed in a striped shape, and the terminal trenchesare formed concentrically. In the semiconductor device, the gate trenchesand the terminal trenchesare positioned in a manner that spacings between the ends of the gate trenchesand the side of the terminal trenchare uniform. That is, the length of the gate trenchesis adjusted according to the curvature of the corners of the terminal trench

Insulated gate semiconductor device

The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region, N+ drain regionP&#x2212; body regionand N&#x2212; drift regionBy excavating part of the upper side of the semiconductor device, a gate trenchis formed. The gate trenchincorporates the gate electrode. A P floating regionis provided beneath the gate trenchA further trenchdiffering in depth from the gate trenchmay be formed, a P floating regionbeing provided beneath the trench

Insulated gate type semiconductor device and manufacturing method thereof

A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t and t , respectively. The wiring layer and the protective film are formed so as to establish a relationship of t <t . An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65&times;10 /&deg; C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.

Growing community of inventors

Toyokawa, Japan

Yasushi Okura