Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Yasushi Okuda

Hiroyuki Doi

Keita Takahashi

Isao Miyanaga

Yoshinori Odake

Nobuyuki Tamura

Toshio Yamada

Shin Hashimoto

Atsushi Fujiwara

Yoshirou Nakata

Yukiharu Uraoka

Masafumi Doi

Kenzou Hatada

Toshiki Mori

Akira Asai

Ichiro Nakao

Ichirou Nakao

Takashi Hori

Ken Mimuro

Youhei Ichikawa

A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate.

Method of manufacturing semiconductor device

A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

Nonvolatile semiconductor memory device and method for driving the same

A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.

Method for fabricating semiconductor device using a CVD insulator film

A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

Nonvolatile semiconductor memory device comprising a memory transistor, a select transistor, and an intermediate diffusion layer

Semiconductor wafer package, method and apparatus for connecting testing

An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

Method for driving a non-volatile semiconductor memory

Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.

Semiconductor memory device and fabrication process

Non-volatile semiconductor memory having an array of non-volatile memory

A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.

Non-volatile semiconductor memory having a ring-shaped floating gate

A method of manufacturing semiconductor devices, which realizes miniaturization, a higher aspect ratio of a via hole, a higher yield and reliability, and a high degree of controllability, by completely filling the via hole by performing heat treatment on an electrically conductive thin film in a vacuum atmosphere. The method involves extending an electrically conductive layer into an electrically insulating layer arranged on the electrically conductive layer including the steps of forming an electrically conductive film on a side wall of a via hole extending in the electrically insulating layer from the electrically conductive layer toward the outside of the electrically insulating layer, and heating the electrically conductive film and the electrically conductive layer so that the electrically conductive film flows into the via hole and the electrically conductive layer projects into the via hole.

Method for extending electrically conductive layer into electrically

A semiconductor device is provided comprising a nonvolatile memory cell through which an LSI and a higher operating speed are achieved. A drain region, an insulating layer partly overlaying the drain region, and a gate electrode formed on the insulating layer are formed on a semiconductor substrate thereby making up a memory cell without a source region. An energy gap between the conduction and valence bands of a semiconductor section including the drain region and the semiconductor substrate is preset to a value corresponding to a first set voltage difference between the drain and the gate. The energy gap between the valence bands (or the conduction bands) of the insulating layer and the semiconductor section at the interface between the semiconductor section and the insulating layer is preset to a value corresponding to a second set voltage difference between the drain and the substrate. Write operations are done by trapping in the insulating layer a charge which has jumped the valence band of the insulating layer at a voltage not less than the second set voltage difference. Read operations are done at a voltage not less than the first set voltage but not more than the second set voltage. Erase operations are done by releasing a charge trapped or by implanting a reverse charge.

Growing community of inventors

Kyoto, Japan

Yasushi Okuda