Fujitsu Corporation

Yasushi Nagano

Minoru Usui

Noriaki Ono

Toru Okabayashi

A data processing device exchanges data between a memory and an external bus master. The memory is connected to the data processing device via a first bus so as to store data. The external bus master is connected to the data processing device via a second bus so as to process data. The data processing device comprises a bus-transmission control unit accessing the memory via the first bus in response to a request to access the memory made by the external bus master via the second bus.

Data processing device accessing a memory in response to a request made by an external bus master

A processing unit has an operation unit and a cache memory, and further has a debug support unit and a non-cache control circuit. The debug support unit outputs a debug mode signal when an address of a program being currently executed and an optional address set for debugging coincide with each other, and the non-cache control circuit controls the operation of the cache memory via the debug mode signal and outputs the debug mode signal externally of the processing unit.

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Kawasaki, Japan

Yasushi Nagano