Mitsubishi Denki Kabushiki Kaisha

Advanced Display, Inc.

Yasushi Matsui

Natsuo Ajika

Hideaki Arima

Atsushi Hachisuka

Kaoru Motonami

Makoto Ohi

Yoshinori Okumura

Tomonori Okudaira

Akio Nakayama

Makoto Ohtani

Kyoko Sawamizu

Hiroyuki Murai

Takafumi Hashiguchi

Yasunori Niwano

Ken Nakashima

Katsuaki Murakami

An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.

Active matrix substrate and its manufacturing method

A display device having a substrate provided with a display region includes a lower layer film formed on the substrate, a transparent conductive thin film formed on the lower layer film and electrically connected thereto, and a protective film formed on the transparent conductive film in a region other than the display region to prevent malformation of the transparent conductive thin film and the lower layer film.

Display device and method with lower layer film formed on substrate but between transparent conductive film and organic layer and then protective film on the transparent film

An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact

A display device includes a scanning line () formed on an insulating substrate; a storage capacitance line () formed in parallel to the scanning line; an image signal line () formed across the scanning line () and the storage capacitance line () through an insulating layer; and a pixel electrode () being surrounded with the scanning line (), the storage capacitance line () and the image signal line (); wherein at least one overlapped area () of the storage capacitance line () and the image signal line () is defined in the area other than the crossing region of the storage capacitance line () and the image signal line () within one pixel area; whereby, breakage of the image signal line is mended without increasing the production steps, and production yield is improved.

Method of mending breakage of line in display device

A method of manufacturing a semitransparent display device includes the steps of forming a light shield film over a transparent display region on a transparent substrate, applying a photosensitive organic film over the transparent substrate coated with the light shield film, exposing and developing the photosensitive organic film to form a through hole extending through the photosensitive organic film in the transparent display region, removing the light shield film exposed through the through hole after forming the through hole, and forming a reflective film above the photosensitive organic film to form a reflective display region. Thereby, such a situation can be prevented that light reflected by a stage after passing through a TFT array substrate causes visible irregularities in thickness of an organic flattening film during exposure processing for forming the organic flattening film.

Transflective display with through hole extending through a light shield in the transmissive region of the display

A semi-transmissive liquid crystal display device is provided with a pixel electrode having in one pixel a reflective electrode reflecting outside light, and a transmissive electrode transmitting light from a back light source, on one of a pair of substrates facing to each other with a liquid crystal film placed in between. The reflective electrode and the transmissive electrode constituting the pixel electrode are formed without having a insulation layer in between. A manufacturing process thereof is simplified by halftone exposure.

Liquid crystal display device and manufacturing method thereof

A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

Method of making a semiconductor integrated device having gate sidewall

A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

Method of manufacturing semiconductor device having interconnection

A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

Semiconductor device having gate electrode spacing dependent upon gate

A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

Method of manufacturing field effect transistor having a multilayer

A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

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Kumamoto, Japan

Yasushi Matsui