Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Yasushi Koubuchi

Masahiro Moniwa

Toshifumi Takeda

Youhei Yamada

Koichi Nagasawa

Jin Onuki

Kunio Miyazaki

Tatsuo Itagaki

Masayasu Nihei

Shinichi Fukada

Jun Sugiura

Masahiro Koizumi

Katsuhiko Shiota

Motoo Suwa

Katuhiko Shiota

Genji Taki

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device

Interconnections are formed over an interlayer insulating film which covers MISFETQformed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device including wiring lines and interconnections

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device, and fabrication process and designing method thereof

A thin film forming method and apparatus, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make Ar ions flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to maintain a stable discharge and perform reverse sputter in a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. An aluminum wiring film whose peak value of x-ray diffraction strength at a (111) plane is 150 Kcps or more is possible. Also, a barrier layer having a layered structure of granular and columnar crystals or a mixed structure thereof providing an efficient barrier effect and a large specific resistance is possible.

Method of and apparatus for sputtering, and integrated circuit device

Growing community of inventors

Kokubunji, Japan

Yasushi Koubuchi