Nec Corporation

Hitachi-lg Data Storage, Inc.

Hitachi-omron Terminal Solutions, Corporation

Yasushi Kinoshita

Atsushi Ochi

Toru Mori

Hirokazu Tohya

Junji Fujita

Hiroshi Yamagishi

Shiro Yoshida

Yoshihiro Fukagawa

Masanori Terao

Hiroshi Wabuka

Eisuke Shiomi

A paper sheet handling apparatus capable of effectively preventing a photodetector from malfunctioning due to external light is provided. The present invention is a paper sheet handling apparatus including a paper sheet handling port, a projector for emitting light within the paper sheet handling port, a photodetector for receiving the light emitted from the projector, and a light-shielding body that is formed along an optical path from the projector towards the photodetector and shields the photodetector against external light; wherein a projector-side end of the light-shielding body is formed to be retracted from an incident direction of the external light towards the photodetector.

Paper sheet handling apparatus

In an optical disc library apparatus having a cartridge storing discs; a drive carrying out recording and playback with respect to the discs; and a robot carrying out disc movements between the aforementioned cartridge and the aforementioned drive; wherein: the periphery of a disc is point restrained in three places during disc movement.

Optical disc library and storage apparatus including disc changer functionality

There is provided an LSI socket containing a pogo-pin type decoupling capacitor for reducing the potential fluctuation of power supplies and GNDs at the time of testing LSI incorporated in a BGA package. The LSI socket comprises a printed boardcontaining decoupling capacitorscorresponding to one or more power supply voltages inside thereof, a pogo-pin supporting casing portionon which the printed boardis overlapped into a single piece, and pogo-pinsinserted into penetrating holes in which hole positions of through holesdrilled in the printed boardand casing holesdrilled in the pogo-pin supporting casing portionare allowed to be matched, wherein the printed boardis disposed on the upper surface side of the pogo-pin supporting casing portionwhich faces the BGA package, or disposed on the lower surface side of the pogo-pin supporting casing portion, at the time of testing the LSI incorporated in the BGA package.

LSI test socket for BGA

A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer formed in a plane shape on a semiconductor substrate, and the shield layer is electrically connected directly to the semiconductor substrate and is fixed to a power supply potential or the ground potential.

Semiconductor integrated circuit

A semiconductor integrated circuit is provided. A semiconductor package having a printed circuit board, a semiconductor chip mounted on a first surface of said printed circuit board, at least one power supply electrode on a second surface of said printed circuit board and connected to at least one power supply terminal of said semiconductor, and at least one ground electrode on a second surface of said printed circuit board and connected to at least one ground terminal of said semiconductor chip; a decoupling capacitor outside said semiconductor package and formed by a power supply plane connected to said power supply electrodes, and a ground plane connected to said ground electrodes; at least one power supply electrode pad connected to said power supply plane; and at least one ground electrode pad connected to said ground plane.

Semiconductor integrated circuit having at least one of a power supply plane and ground plane divided into parts insulated from one another

An n-channel type MIS field effect transistor is fabricated on a p-type well defined in a standard p-type silicon substrate, and is expected to respond to a high-frequency signal, wherein a heavily-doped p-type well contact region is formed outside of the p-type well for increasing the substrate resistance, and a capacitor is coupled to the heavily-doped p-type well contact region for increasing the impedance so that the insertion loss is reduced by virtue of the large impedance of the silicon substrate.

Semiconductor device with high-speed switching circuit implemented by MIS transistors and process for fabrication thereof

A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.

Bipolar transistor having lightly doped epitaxial collector region constant in dopant impurity and process of fabrication thereof

The electromagnetic interference suppressing device of the present invention includes a plurality of connection layers and ground layers formed of a conductive material. The connection layers and the ground layers are alternately layered. Insulating layers, formed of an insulating material, intervene between the neighboring connection layers and ground layers. The odd connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end. The even connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end opposite to the odd connection-layered end. The bottommost connection layer is connected to a first signal terminal. The uppermost connection layer is connected to a second signal terminal. The ground layer is connected to a ground terminal.

Electromagnetic interference suppressing device and circuit

A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Semiconductor integrated circuit device and method of designing same

Process of fabricating a bipolar transistor having lightly doped epitaxial collector region constant in dopant impurity

An integrated circuit structure comprises a conductor film that serves as a passive element or an interconnection, and a silicon substrate. A cavity is disposed between the substrate and the conductor film and thus underneath the conductor film. The substrate is formed by forming an island of oxide film in a surface of the substrate, and then wet etching the island from the surface of the substrate thereby forming the cavity.

Integrated circuit structure with a gap between resistor film and

To provide a check pattern whereby whether via-hole openings are made correctly or not can be examined without needing high precision positioning of the via-holes, a check pattern of the invention comprises: a check wiring (3) configured on a semiconductor substrate (2), an insulation film (4) formed on the semiconductor substrate (2) to cover the check wiring; and a pair of via-holes (6) each configured at each end of the check wiring (3), said each (6) positioned slightly shifted inversely with each other from a center line in a width direction of the check wiring (3), and a bottom of said each (6) being positioned to traverse both the check wiring (3) and the insulation film (4).

Check pattern for via-hole opening examination

There are formed simultaneously a first conductive layer selectively on a region of a semiconductor substrate in which an N-channel MOS transistor is to be formed and on a region of the semiconductor in which a p-channel MOS transistor is to be formed, a second conductive layer on a region of the semiconductor substrate in which a capacitive element is to be formed, and a third conductive layer on a region of the semiconductor substrate in which the resistive element is to be formed. Next, there are formed simultaneously a first insulating film on the lateral side of the first conductive layer, a second insulating film selectively on the second conductive layer, and a third insulating film selectively on the third conductive layer. Then the fourth insulating film is formed on the whole surface. Thereafter there are formed simultaneously a fifth conductive layer on a region of the semiconductor substrate in which a bipolar transistor is to be formed, and a sixth conductive layer on the fourth insulating film on the second conductive layer.

Method of manufacturing a semiconductor device having MOS transistor and

In a semiconductor device having a PN junction element separating region, in order to reduce a width of the PN junction element separating region without sacrifice of a punch-through breakdown voltage of the PN junction element separating region, the PN junction element separating region is composed of an upper impurity layer of a first conductivity type having low impurity density and a lower impurity layer of the first conductivity type having a high impurity density and a width of the upper impurity layer is smaller than a width of the lower impurity layer.

Growing community of inventors

Tokyo, Japan

Yasushi Kinoshita