Hitachi Device Engineering Co., Ltd.

Hitachi, Ltd.

Renesas Technology Corp.

Other

Renesas Electronics Corporation

Hitachi Ulsi Engineering Corp.

Rising Silicon, Inc.

Yasushi Kawase

Takesada Akiba

Masashi Horiguchi

Goro Kitsukawa

Tsugio Takahashi

Yoshinobu Nakagome

Kazuhiko Kajigaya

Masayuki M Nakamura

Yoshikazu Saitoh

Hideharu Yahata

Kazuyoshi Shiba

Naoki Miyamoto

Masayuki Nakamura

Susumu Ishida

Yasushi Nagata

Takao Watanabe

Takayuki Kawahara

Masakazu Aoki

Yoshiki Kawajiri

Shinichi Miyatake

Goro Sakamaki

Yasuhiro Kasama

Toshikazu Tachibana

Kazuya Endo

Yoichi Matsuno

Tathunori Mushya

The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

Semiconductor integrated circuit device for driving liquid crystal display

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed

Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha=Cp (VCI&#x2212;VCOML)/&#x394;t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha=Cp (VCOMH&#x2212;VCI)/&#x394;t. Accordingly, power consumed by Ichais the reference voltage VCI&#xd7;Icha, and power consumed by Ichais VCI&#xd7;Icha&#xd7;2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis=Cp (VCOMH&#x2212;GND)/&#x394;t, and a discharging current from the ground potential GND to the second voltage VCOML, Idis=Cp (GND&#x2212;VCOML)/&#x394;t. Now, if converted in terms of power consumed at the reference voltage VCI, since Idisrepresents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis, is VCI&#xd7;Idis

Liquid crystal drive device

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Semiconductor memory device

A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.

Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Semiconductor memory

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Semiconductor integrated circuit

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.

Growing community of inventors

Tachikawa, Japan

Yasushi Kawase