Fujitsu Corporation

Other

Advanced Micro Devices Corporation

Spansion Llc.

Fujitsu Vlsi Limited

Yasushi Kasa

Takao Akaogi

Shouichi Kawamura

Kiyoshi Itano

Hiromi Kawashima

Yasushige Ogawa

Tiao-Hua Kuo

Johnny C Chen

Nobuaki Takashina

Nancy S Leong

Minoru Yamashita

Masanobu Yoshida

Michael Van Buskirk

Tetsuji Takeguchi

Ryoji Hagiwara

Hisayoshi Watanabe

Hirokazu Yamazaki

Sinsuke Kumakura

Guowei Wang

Kazuhiro Kurihara

Kazunari Kido

Fan W Lai

Yuji Arayama

Yoshihiro Takemae

Michael Allen Van Buskirk

Trung S Pham

Hiroaki Wada

Shigekazu Yamada

Tsutomu Nakai

Yong K Kim

Masanori Nagasawa

Yoshihiro Tsukidate

Yuichi Einaga

Andy Cheung

Vikram S Santurkar

Sunao Araki

Johnny Chung-Lee Chen

Jyoji Kato

Seiji Hirayama

Akira Terui

Yasushige Oqawa

Takao Akagoi

Ming-Huei Shing

Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level

Error correction scheme for non-volatile memory

Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level.

A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (), a program layer () provided over the pair of metal interconnections (B, C) and in which an opening () may be selectively formed in the program layer () on the basis of programming information, and a read circuit () reading the programming information by determining whether such an opening () is formed in the program layer () by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer () may be made of a material having a dielectric constant higher than that of air or the program layer () may be made of a conductor or a material having a dielectric constant lower than that of air. Thus, trimming information or information on a device identification (ID) can be stored, even if the semiconductor device is a logic device that does not have a memory transistor, by detecting the information that is determined by the electrostatic capacitance that varies depending on whether or not there is provided an opening ().

Semiconductor device and programming method therefor

The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Semiconductor device and programming method

A nonvolatile semiconductor memory device includes a plurality of blocks each having a nonvolatile memory cell array, and a program potential generating circuit which supplies a program potential to the nonvolatile memory cell array, wherein the program potential generating circuit adjusts the program potential according to a first address signal selecting one of the blocks and a second address signal indicating a position of a write-accessed memory cell in the noted one of the blocks.

Nonvolatile semiconductor memory device supplying proper program potential

A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address. Regardless the result of redundancy judgment on whether the supplied address matches the redundant address indicating the defective sector, a regular sector in the first block and the spare sector in the second block, to be a pair thereof, are set to selected status simultaneously during the first period when access operation stars, so a drop in access speed due to a redundancy judgment operation can be suppressed.

Memory circuit with redundant configuration

A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

OTP sector double protection for a simultaneous operation flash memory

A semiconductor memory device includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells, each formed of a MIS transistor, are disposed at intersections of the word lines and the bit lines. The threshold voltages of the MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof. The floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells. A first row decoder applies a normal voltage to a selected word line to select memory cells connected to the selected word line, when reading data. A second row decoder applies a predetermined source voltage to sources of memory cells connected to the selected word line, and applies an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.

Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture

A semiconductor memory device has 2 word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2 (n>m) word lines among the 2 word lines, and a second unit for not selecting a block of 2 (m>k) word lines among the 2 word lines. The second unit does not select the block of 2 word lines, and selects a block of 2 word lines prepared outside the 2 word lines when any one of the 2 word lines among the 2 word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

Multiple purpose bus for a simultaneous operation flash memory device

Nonvolatile semiconductor memory has a core-side cell array having word lines, bit lines and memory cells; a reference-side cell array having word lines, bit line, and reference cell; and, a sense amplifier which compares a core-side input voltage corresponding to a bit line current in the core-side cell array, and a reference-side input voltage corresponding to the bit-line current in the reference-side cell array. The core-side decoder-driver and reference-side decoder-driver drive the core-side and reference-side word lines to the power supply voltage at a first time at the end of the address change detection pulse, and, at a second time a prescribed time after the end of the address change detection pulse, drive the core-side and reference-side word lines to a boost voltage level higher than the power supply voltage. The sense amplifier begins comparison of the core-side and the reference-side input voltages after the second time.

Nonvolatile semiconductor memory with improved sense amplifier operating margin

Growing community of inventors

Kawasaki, Japan

Yasushi Kasa