Kabushiki Kaisha Toshiba

Yasushi Kameda

Makoto Segawa

Ken Takeuchi

Takuya Futatsuyama

Koichi Kawai

Hitoshi Shiga

Nobuaki Otsuka

Kikuko Sugimae

Kenichi Nakamura

Osamu Hirabayashi

Takayuki Harima

Hiroshi Takamoto

Hiroshi Hatada

A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode.

Semiconductor device and method of manufacturing the same

The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Non-volatile semiconductor memory device

A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and second switching elements. The data cache, clamp circuit and first and second switching elements are controlled by use of a control circuit and the bit line to which a memory cell of an address to be written is connected is precharged by use of the clamp circuit or data cache and the other bit line is shielded by the clamp circuit.

Electrically rewritable nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes write/verify circuits, a switching elements which divides the bit lines into plural portions, and a control circuit. The control circuit is configured to control the write/verify circuits and switching elements. The control circuit performs a control operation to perform the write and verify operations with the switching elements set in an OFF state when a memory cell of an address to be written lies on the write/verify circuit side in the memory cell array, write and save data into a memory cell lying on the write/verify circuit side with the switching elements set in the OFF state when the memory cell lies farther apart from the write/verify circuit than the switching elements, and then turn ON the switching elements while the write/verify circuit is not being operated and write the saved data into a memory cell of an address to be written.

Nonvolatile semiconductor memory device and write/verify method thereof

A semiconductor device has an internal circuit ( ), a PAD, a NMOS Tr (QN) as a protective transistor formed between a node (N) on a signal line and a first power source (Vss), and a NOR gate (G ) as a logical gate connected to a gate as a control terminal of the NMOS transistor (QN). The internal circuit ( ) is connected to the PAD through the signal line. The NOR gate (G ) keeps the protective transistor (QN) an OFF state during a normal operation of the internal circuit ( ). In addition, the semiconductor device further includes a test circuit ( ). The output from the NOR gate (G ), whose one input is the output from the test circuit ( ), is supplied to the gate of the NMOS transistor (QN). The output from the test circuit ( ) is thereby output to outside through the NMOS transistor (QN) and the PAD.

Semiconductor device having protective and test circuits

A semiconductor device has pads that are arranged in such a manner as to easily accept manual needles to carry out a test. This technique is applicable to carry out a test with use of a boundary scan test circuit in synchronization with a cycle time defined by a normal operation clock signal. The semiconductor device has a first pad connected to a first one of registers that form a serial scan chain, to supply test data to the registers, a second pad connected to a last one of the registers, and a third pad to supply a test clock signal to the registers. The registers are arranged in a central part of the semiconductor device, and the first to third pads are arranged at the periphery of the semiconductor device.

Semiconductor device with test circuit

A semiconductor device has an output buffer having transistors connected in parallel for an external driving purpose, a connection terminal connected to an external resistor, and an output impedance controller connected to the connection terminal and the output buffer, for adjusting the impedance of the output buffer in accordance with the external resistor. The output impedance controller has a first transistor of a first conductivity type having a drain connected to the connection terminal; a first level-controller connected to a gate of the first transistor, for controlling the level of the gate of the first transistor to set the connection terminal to a predetermined voltage level; a second transistor having a gate connected to the gate of the first transistor and a source connected to a source of the first transistor; a first dummy transistor group consisting of transistors that are of a second conductivity type, are connected to the second transistor, correspond to the output buffer transistors, and are connected in parallel; a first controller connected to the second transistor and the first dummy transistor group, for controlling the first dummy transistor group to equalize the level of a connection node between the second transistor and the first dummy transistor group with the predetermined voltage level; and a second controller for controlling the output buffer transistors according to the control carried out by the first controller.

Semiconductor device

A semiconductor device is provided with at least one transistor formed on a semiconductor substrate, the transistor being provided with a conductive sidewall spacer, and at least one conductive film formed so as to face a gate of the transistor via an insulative film, the conductive film covering at least an entire region of a gate region of the transistor and acting as a capacitor electrode. The conductive sidewall spacer and the conductive film are connected together. A potential is supplied to the conductive sidewall spacer and the conductive film, the potential being different from a potential of the gate of the transistor.

Semiconductor device provided with LDD transistors

A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

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Yokosuka, Japan

Yasushi Kameda