Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Yasushi Gohou

Shunichi Iwanari

Yasuo Murakuki

Hiroshige Hirano

Takashi Miki

Masahiko Sakagami

Kunisato Yamaoka

Tetsuji Nakakuma

Yoshihisa Kato

Masahiro Nakanishi

Masayuki Toyama

Masanori Matsuura

Yoshiaki Nakao

A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

Semiconductor memory device and semiconductor memory system

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cellin the memory corecorresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

Semiconductor memory device

A memory system of the present invention includes a memory device having a nonvolatile memory and an access device which accesses the memory device. The memory device has a detection unit to detect a temperature of the memory device, a determination unit to determine an operating condition in accordance with the detected temperature and a notification unit to notify the access device of the determined operating condition. The access device has an interface unit to connect to the memory device and a controlling unit to control the interface unit in accordance with the notified operating condition from the memory device.

Memory system

A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM; a counter; a CAMthat judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM; a storage control unitthat, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAMthat corresponds to the count value indicated by the counter; and a counter control unitthat causes the counterto update the count value each time a result of the judgment is negative.

Semiconductor storage apparatus

An operation switch circuit receives a command specifying operational specifications from a host. An operation control circuit controls the time of voltage application to a plate line based on an output signal from the operation switch circuit, to attain volatile-mode operation in a first memory region and nonvolatile-mode operation in a second memory region, for example.

Ferroelectric memory device

A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Ferroelectric memory and method for reading data from the ferroelectric memory

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell, in the memory core, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage areaformed from electrically-rewritable nonvolatile memory and a second setting function storage areaformed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address registerand transfer of operation mode setting information to an operation mode registerare selectively performed.

Growing community of inventors

Osaka, Japan

Yasushi Gohou