Sony Corporation

Sony Computer Entertainment Inc.

Sony Group Corporation

Other

Philips Electronics N.v.

Yasushi Fujinami

Makoto Kawamura

Toshiya Hamada

Kenichi Nakanishi

Jun Yonemitsu

Hideaki Okubo

Yoichi Yagasaki

Keiichi Tsutsui

Ken Ishii

Naohiro Adachi

Tatsuo Shinbashi

Motoki Kato

Ryoji Ikegaya

Tatsuya Kakumu

Katsumi Tahara

Lui Sakai

Hiroyuki Iwaki

Teruhiko Suzuki

Katsuji Igarashi

Koji Ihara

Shusuke Utsumi

Hideki Koyanagi

Tomoyuki Sato

Markus H Veltman

Akihiko Ueda

Makiko Yamamoto

Kuniaki Takahashi

Hiroyuki Yamagishi

Takenori Ohshima

Ryuichi Iwamura

Yoshinori Shimizu

Yoshiyuki Akiyama

Tomihiro Nakagawa

Goro Hayakawa

Tetsuya Yamamoto

Yusuke Oike

Shoji Tanaka

Ken Kutaragi

Wiebe De Haan

Kiyoshi Ohsato

Kenichi Imai

Tsunenori Shiimoto

Haruhiko Terada

Tomohiro Matsumoto

Toru Okazaki

Tetsuya Hirano

Yoshiyuki Shibahara

Akito Sekiya

Hakaru Tamukoh

Takashi Morie

Kentarou Mori

Matatoshi Honjo

Quan Wang

A signal processing circuit outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.

Signal processing circuit, signal processing device, and signal processing method using logic circuit

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation system, and multiply-accumulate operation method

A multiply-accumulate device () includes: a comparison unit () that compares, with a threshold voltage, a voltage generated by an electric charge stored in a storage unit (), and outputs an output signal at timing at which the voltage exceeds the threshold voltage; and a control circuit () that reduces, based on a predetermined set value, a charging current to the storage unit () from a plurality of input units () connected to the storage unit ().

Multiply-accumulate device and multiply-accumulate method

A multiply-accumulate system () includes: a statistic calculation unit () that executes a standardization calculation for an input signal; and a multiply-accumulate device () that executes multiplication-accumulation based on the standardized input signal.

Multiply-accumulate system and multiply-accumulate method

The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

Memory controller, storage device, information processing system, and memory control method

The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

Memory controller, memory system, and information processing system

[Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Memory controller, memory system, and memory controller control method

To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.

Memory controller, information processing system, and memory extension area management method

A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

Encoding device, memory controller, communication system, and encoding method

Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Storage control apparatus, storage apparatus, and storage control method

The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.

Memory controller, storage apparatus, information processing system, and method for controlling nonvolatile memory

A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.

Storage device, storage system, and method of controlling storage device

There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.

Storage apparatus, memory controller, control method for storage apparatus, and program

A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Storage control apparatus to control pre-processing operations

Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

Interface control circuit, memory system, and method of controlling an interface control circuit

Growing community of inventors

Tokyo, Japan

Yasushi Fujinami