Nec Corporation

Yasushi Amamiya

Hidemi Noguchi

Yasuyuki Suzuki

Junichi Abe

Kenichi Hosoya

Tomoyuki Yamase

To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D convertersamples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSPdemodulates the digital signal converted by A/D converterand computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuitextracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuitadjusts the phase of the clock signal extracted by sampling clock extraction circuitto the phase computed by DSPand generates a clock signal having the adjusted phase as the sampling clock signal.

Receiving device and demodulation device

An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n&#xd7;M+1) sampling signal; and a control unit that compares, for each period of (n&#xd7;M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

A/D conversion device and compensation control method for A/D conversion device

A logic circuit is provided with a first differential transistor pair (Q, Q) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q, Q); a first transistor (Q) connected between a common emitter of the first differential transistor pair (Q, Q) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit () connected to a first junction between the common emitter of the first differential transistor pair (Q, Q) and a collector of the first transistor (Q), for stabilizing a potential at said first junction.

Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit

In the present invention, a logic circuit is provided therein with a current supply control circuit for controlling the amount of current supplied to a differential circuit. This current supply control circuit comprises a bypass path for bypassing the current around the differential circuit, a switching transistor interposed in the bypass path for opening/closing the bypass path in accordance with the signal level of a clock signal applied thereto from the outside, and a current amount control transistor for controlling the amount of current supplied to the differential circuit. The current amount control transistor adjusts the amount of current in accordance with the signal level of the clock signal. The current amount control transistor is configured to ensure a sufficient amount of current when current flows into the differential circuit in response to the clock signal, and to sufficiently reduce the amount of current that flows into the bypass circuit, thus reducing the amount of current leaking to the differential circuit when current flows into the bypass circuit.

Logic circuit with restrained leak current to differential circuit

This preamplification circuit comprises a first circuit section, second circuit section the input signal of which is the output signal of the first circuit section, and third circuit section which is connected with the input section of the first circuit section and consumes a part of the current to be inputted to a connection point with the input section of the first circuit section and has the capacitance value of the third circuit section set at a value for suppressing a gain peaking of gain frequency characteristics which occurs in the preamplification circuit.

Preamplification circuit

A semiconductor integrated circuit including interconnect for connecting a current switch circuit and an emitter follower circuit and a method for producing the semiconductor integrated circuit. A matching between a characteristic impedance of the interconnect and an output impedance of the current switch circuit at its output and also an input impedance of the emitter follower circuit at its input in a predetermined frequency range is conducted to prevent an occurrence of distortion of a waveform of a data signal and a gain peaking of frequency characteristic. An impedance converter circuit can be placed at the input or output of the interconnect to match the characteristic impedance of the interconnect.

Semiconductor integrated circuit and manufacturing method thereof

An obstacle is opposed to a lower electrode of a metal-insulator-metal capacitor so as to form a gap therebetween, thereafter, insulating material is deposited so as to fill the gap and form a dielectric layer of the metal-insulator-metal capacitor; even if the deposition does not achieve a conformal step coverage, the insulating material in the gap surely isolates the lower electrode from the upper electrode, and the lower electrode is never short-circuited with the upper electrode.

Capacitor with obstacle between side surfaces of lower electrode and

A heterojunction bipolar transistor (HBT) has shortened electron transport time through collector region over wide range of biased conditions. The HBT is expected to exhibit enhanced high frequency characteristics. In operation under biased condition, a portion of an n-GaAs collector layer makes a depletion region. A p-GaAs base contact layer is in contact with side surface of the depletion region. Even if the collector layer remains in the n-type, the contour of band potential in conduction band of the collector depletion region is adjusted to a desired one by controlling electric potential of the base contact layer. As a result, the band potential with smooth slope is created in the collector depletion region, shortening transport time through the collector layer. The intrinsic portion of the collector layer is of the n-type so that occurrence of Kirk effect is suppressed, ensuring enhanced high frequency characteristics.

Bipolar transistor

In a bipolar transistor including a semi-insulating substrate, a collector layer formed on the semi-insulating substrate and a base layer formed on the collector layer, a base contact layer is in contact; with a part of a lower surface of the base layer.

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Tokyo, Japan

Yasushi Amamiya