Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Engineering Co., Ltd.

Yasushi Akao

Shiro Baba

Kouki Noguchi

Shumpei Kawasaki

Keiichi Kurakazu

Shigeki Masumura

Kaoru Fukada

Mitsuru Watabe

Hiroshi Ohsuga

Eiji Sakakibara

Takanaga Yamazaki

Toshimasa Kihara

Kiyoshi Matsubara

Takashi Tsukamoto

Yugo Kashiwagi

Masahiro Kainaga

Yoichi Asano

Katsuhiko Ishida

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Toru Baji

Atsushi Kiuchi

Koki Noguchi

Terumi Sawase

Atsushi Hasegawa

Hideo Nakamura

Yoshitaka Ito

Akio Hayakawa

Hironobu Hasegawa

Yoshimune Hagiwara

Kenichi Kuroda

Kazufumi Suzukawa

Yuji Hatano

Kunihiko Nakada

Haruo Keida

Shinkichi Hotta

Isamu Mochizuki

Hisao Sasaki

Takeshi Miyazaki

Yoshiyuki Miwa

Koyo Katsura

Hideo Maejima

Takashi Totsuka

Takayuki Tamura

Nagamasa Mizushima

Susumu Matsui

Jun Kitahara

Toshio Okochi

Toru Owada

Kenji Kawakita

Jiro Kashio

Matsuaki Terada

Takeshi Kataoka

Shirou Baba

Yuji Sato

Takeshi Asahi

Kazuo Naito

Shinichi Sawamura

Hiroyuki Hatori

Tatsuya Aizawa

Kazumasa Kishi

Yosuke Murayama

Mitsuhiro Miyazaki

Tatsuo Nakai

Masayasu Ohizumi

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural areas which store user data, and restricts access to the user data from a host computer and also dynamically changes an area an access to which is to be restricted. Accordingly, the ease of use of the external storage device for the host computer is improved. Specifically, the interior of the flash memory is divided into a normal area not protected by a password or the like and a protected area protected by a password or the like. A microprocessor controls accesses to the normal area and the protected area in accordance with a command from the host computer. In addition, the host computer can access the protected area after passing through authentication using a password. Moreover, the host computer changes information indicative of the location of the protected area, thereby dynamically changing the protection area.

External storage device using non-volatile semiconductor memory

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Data processing device having a central processing unit and digital signal processing unit

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions

A built-in memory is divided into the following two types: first memories and and second memories and , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core can simultaneously transfer two data values from the built-in memory to a DSP engine . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core can access an external memory in parallel with the access to the second memories and and the first memories and

A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

Semiconductor integrated circuit device

A data processor including a central processing unit and a plurality of direct map cache memories ( ) has a plurality of area designating circuits ( ) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.

Data processor and data processing system

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Growing community of inventors

Kokubunji, Japan

Yasushi Akao