Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Limied

Yasurou Matsuzaki

Masao Taguchi

Hiroyoshi Tomita

Takaaki Suzuki

Yasuharu Sato

Yoshihiro Takemae

Masao Nakano

Toshiya Uchida

Kenichi Kawasaki

Naoharu Shinozaki

Yasuhiro Fujii

Masafumi Yamazaki

Atsushi Hatakeyama

Tadao Aikawa

Miki Yanagawa

Shinya Fujioka

Yoshinori Okajima

Hitoshi Ikeda

Masato Matsumiya

Hirohiko Mochizuki

Shinnosuke Kamata

Nobutaka Taniguchi

Koichi Nishimura

Kotoku Sato

Ayako Sato

Akihiro Funyu

Hiroko Douchi

Kimiaki Satoh

Yuji Tsuchimoto

Masahiko Saitou

Terumasa Kitahara

Masahiro Sato

Masataka Mizukoshi

Masaki Takahashi

Akira Takashima

Tatsuya Kanda

Kouji Ueno

Makoto Yanagisawa

Tetsuya Hiraoka

Nobumi Kodama

Hidehiko Akasaki

Hiroyuki Fujimoto

Takahiro Suzuki

Waichirou Fujieda

Kaname Ozawa

Kazuyuki Aiba

Yukihiro Nomura

Toyonobu Yamada

Tsuneo Funatsu

Masami Matsuoka

Junji Akaza

Hirohisa Mizuno

Takashi Imura

Yoshikazu Mutoh

A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Multi-port memory based on DRAM core

In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Semiconductor apparatus having a large-size bus connection

A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

Semiconductor device with circuitry for efficient information exchange

A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

Semiconductor phase adjustment system module

A memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. When a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function

According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

Memory circuit with automatic refresh function

A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

Semiconductor memory

Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

Semiconductor memory with single cell and twin cell refreshing

A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.

Deformable semiconductor device

A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.

Test apparatus for semiconductor device

Growing community of inventors

Kawasaki, Japan

Yasurou Matsuzaki