Yamaha Corporation

Yasuomi Tanaka

Nobuaki H Tsuji

Hirotaka Kawai

Masao Noro

Masaya Suzuki

A controllerupdates data LVLm indicative of a level section of an input audio signal and controls a reference level Vr based on a signal CMP representative of a comparison result between the input audio signal and the reference level Vr, and further, controls gains of electronic volumesL andR in such a manner that these gains become such gains corresponding to the level section of the input audio signal. In this case, the level sections of the input audio signals are related to the gains in such a manner that levels of output signals of the electronic volumes do not exceed a previously set output amplitude upper limit level.

Automatic gain control circuit

A pulse monitor circuit detects the presence or non-presence of the output pulses output from an output stage circuit. The pulse monitor circuit outputs an up signal to the up/down counter when the output pulses do not exist at all and outputs a down signal to the up/down counter when the output pulses exist. The up/down counter outputs a signal for increasing the delay amount of a delay amount variable circuit when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit.

Class D amplifier circuit

A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.

Offset voltage correction circuit and class D amplifier

A spectrum spreading circuit, includes a control portion that repeats a sequence in which the control portion generates a designation signal for designating all of plural frequencies in prescribed order by selecting a next frequency from the frequencies which have not been selected, and a signal generating portion that sequentially generates output signals having the designated frequencies respectively on the basis of the designation signal.

Spectrum spreading circuit

A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.

Comparator

An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.

A complementary signal generating circuit () generates first complementary signals (SS) from a PWM signal. A signal converting circuit () converts the first complementary signals to second complementary signals (S, Sor S, S) having a voltage component based on a negative power supply (VPP&#x2212;). Among the second-complementary signals, the signals (S, S) are supplied to a driving circuit (), and the signals (S, S) are supplied to a current driving circuit (). In response to the signals (S, S), the current driving circuit outputs third complementary signals (H, H) having a current component that is directed toward the negative power supply (VPP&#x2212;), to a driving circuit (). As a result, the driving circuits () complementarily drive power-MOS transistors ().

Class D amplifier

A detecting circuit (REFH, CM, LA, TN, RN) which detects an overcurrent flowing through a power-MOS transistor () in an output stage to output a first signal (ITN) is disposed in a first driving circuit (H) on the side of a high-side driver. Another detecting circuit (REFL, CM, LA, TN, RN) which detects an overcurrent flowing through a power-MOS transistor () in the output stage to output a second signal (ITN) is disposed in a driving circuit (L) on the side of a low-side driver. The first signal (ITN) is converted to a third signal (ITT) based on a negative power supply (VPP&#x2212;), by a signal converting circuit. The third signal is added to the second signal. In response to the addition signal, a pulse signal to be input to the driving circuits (H andL) is blocked.

A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level. Thus, it is possible to stabilize the write word line in level because its adjoining write word line hardly interferes with the write word line at a random-access mode. In addition, by reducing the duration in writing of data into the memory cell, it is possible to prevent charges accumulated in the memory cell from easily leaking onto the write bit line.

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Hamamatsu, Japan

Yasuomi Tanaka