Other

Asahi Kasei Kogyo Kabushiki Kaisha

Sharp Kabushiki Kaisha Corporation

Nissan Motor Company Limited

Nippon Precision Circuits Inc.

Yasuo Tarui

Kazuo Sakamaki

Tadahiko Hirai

Satoshi Tanimoto

Shinichi Morita

Yoshihiro Soutome

A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.

Transistor-type ferroelectric nonvolatile memory element

A ferroelectric body transistor having a structure of MFMIS (conductor film) -ferroelectric film-conductor film-insulating film-semiconductor) including a gate insulator capacitor having an MIS structure, a low dielectric constant layer restraining layer interposed between an insulating film made of a material having a high inductive capacity of CeO and a semiconductor substrate to thereby restrain a low dielectric constant layer of SiO or the like from being produced at an interface between the insulating film and the semiconductor substrate and restrain a capacitance from being reduced. An area of the gate insulator capacitor can be reduced and highly integrated formation is provided.

Transistor type ferroelectric body nonvolatile storage element

Ferroelectric memory element having an MFIS structure including a silicon semiconductor substrate and an insulating film arranged above the silicon semiconductor substrate. The insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film so that an unnecessary, low dielectric constant layer is prevented from forming between the semiconductor substrate and the insulating film. A ferroelectric film is arranged on the insulating film. The low dielectric constant layer restraining film is thinner than the ferroelectric film.

Ferroelectric memory element

An Si oxide film, an oriented paraelectric oxide thin film and an oriented ferroelectric thin film are laminated on an Si single crystal substrate having a region for a source and a drain. A conductor thin film is formed in a portion not covered with an insulating film. A laminated structure formed of the Si oxide film, the oriented paraelectric oxide thin film and the oriented ferroelectric thin film is used as a gate of a transistor. The Si oxide film functions as a carrier injection inhibiting layer.

Semiconductor storage device and method for manufacturing the same

A ferroelectric thin film is produced on a substrate placed in an oxygen gas atmosphere within a reaction chamber. Evaporated source materials (organic metal compounds) are separately introduced in a predetermined sequence into the reaction chamber to produce a PZT or PLZT layer structure having an estimated stoichiometric composition. This cycle of introduction of the source materials is repeated continuously to produce a PZT or PLZT ferroelectric thin film having a predetermined number of PZT or PLZT layer structures piled on the substrate.

Growing community of inventors

Higashikurume-shi, Tokyo, Japan

Yasuo Tarui