Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Automotive Systems, Ltd.

Yasuo Sugure

Yasuhiro Ito

Akihiko Hyodo

Tetsuya Yamada

Hiromichi Yamada

Hideaki Kurata

Takanaga Yamazaki

George Saikalis

Shigeru Oho

Donald James McCune

Sujit S Phatak

Takeshi Kataoka

Shogo Nakao

Yoshinobu Fukano

Kenta Morishima

Seiji Takeuchi

Tomomi Ishikura

Kazuya Hirayanagi

A processor acquires a plurality of test items for a simulation model of a target system, each test item including at least one event; detects a set of test items from the plurality of test items under an aggregation condition in which an event in the set is not dependent on an event in another test item in the set; includes a common event, which is an event in the set that is the same as an event in another test item in the set, in an aggregate test item while avoiding overlapping of the common event, and includes a unique event, which is an event in the set that differs from events in other test items in the set, in the aggregate test item; and executes a simulation using the simulation model in accordance with the aggregate test item.

Computer system, test method, and recording medium

A fault simulation system that has a simulation unit comprising an ECU model including an element fault model made to have a fault by a time setting or external command and all or a portion of a sensor model, actuator model, vehicle model, and driver model and can evaluate vehicle behavior at the time of an element fault according to driving operation based on a set travel scenario, wherein the passage time, vehicle behavior, driving operation, and the like, at each point on a course are determined through non-fault simulation and on the basis of that information, an element fault is inserted according to a fault time setting or fault command for the element fault model.

Fault simulation system

Temporary fault injection to existing hardware is performed using only software without changing an implementation of the hardware. A fault injection interrupt process starts on an operation of a CPU using an interrupt that is not used by software, and an internal state of hardware is updated to the same value as a result obtained when a fault has occurred during the interrupt process. A clock of the CPU during the interrupt process is accelerated so that a period of time of the interrupt process is smaller than a period of time until a fault becomes effective.

Microcontroller fault injection method and system

Provided is a malfunction influence evaluation system comprising a controller simulator that simulates the operation of a controller, an input apparatus that provides input data to the controller simulator, a simulation manager that exercises integrated management of the operation of the input apparatus and the controller simulator, and a database wherein malfunction information and simulation conditions to be referred to by the simulation manager is stored. The controller simulator retains a control program for the controller and an analysis unit, and the analysis unit has a propagation flag tracking function wherein propagation flags are assigned to a variable within the control program, bits of the variable are set by inputting a prescribed value thereto as a malfunction input value, the bits are propagated each time the variable is involved in a calculation within the control program, the states of propagation of the bits are tracked, and the result thereof is output.

Malfunction influence evaluation system and evaluation method using a propagation flag

The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

Computer system, program, and method for assigning computational resource to be used in simulation

A method and apparatus for developing multicore microcomputer-based systems. A dual core controller model having at least one parameter is simulated and, similarly, a plant model having at least one parameter and controlled by the controller model is also simulated. The user interface then has access to the parameters of the controller model and plant model and optionally suspends execution of the controller model and plant model in response to a trigger event. The user interface determines the status of the various controller model parameters for both cores and/or plant model parameters at the time of the trigger without altering the controller model parameters or the plant model parameters. The core parameters for both cores are displayed on a display device.

Apparatus and method to develop multi-core microcomputer-based systems

In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.

Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors

The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

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Tokyo, Japan

Yasuo Sugure