Sony Corporation

Yasuo Sakura

Shiro Miyagi

Mitsushige Tatami

Tetsuro Nakata

Yasutaka Kotani

Yoshinori Suzuki

Noboru Fujii

Masao Hara

A PLL circuit which is used as a reproducing clock forming circuit of a digital signal reproducing apparatus. The PLL circuit is strong against noises and has stable characteristics. Comparison outputs of a phase comparator 3 are outputted in a form of balance (differential) signals and are supplied to a loop filer 4. Output signals of the loop filter 4 are supplied to control voltage input terminals of a VCO 5 in a form of the balance signals. In-phase components of the noises included in control voltages can be cancelled. Time constants of the loop filter can be switched by bipolar transistors Tr31 and Tr32. A balance of the balance signals is not broken by base currents of the transistors Tr31 and Tr32.

PLL circuit and digital signal reproducing apparatus

In a color video signal processing circuit for use in processing two chrominance component signals produced on the reproduction side of a video tape recorder, in which two chrominance component signals have been time compressed and successively recorded in cyclically repeated fashion as one series of chrominance signal, such a signal is time expanded and made into two series of chrominance signals on the reproduction side. Each of the two series of chrominance signals, i.e., the current signal, and the signal 1H before each are subjected to digital processing for detection of a correlation therebetween and an arithmetical mean value of both the signals is output when there is such a correlation and also the level of the current signal is higher than a reference level, whereas the current signal is output as it is when the level of the current signal is lower than the reference level or when there is no such correlation even if the level of the current signal is higher than the reference level.

Circuit for processing color video signal

A time base error corrector comprises a chrominance subcarrier phase corrector whereby the subcarrier phase of a video signal is controlled before being written in the buffer memory in such a way that when the video signal is read from the buffer memory on the basis of the reference video signal, the subcarrier phase of the read video signal may match that of the reference video signal. In the NTSC system, the succeeding line odd/even (O/E) identification is predicted on the basis of a content O/E of the preceding field identification and a content O/E of the preceding field top line identification, and a non-inverted return subcarrier signal is generated when the succeeding top line identification is determined to be odd but an inverted return subcarrier signal RSC is generated when determined to be even. In the system, the succeeding line O/E odd/even and I/N inversion/non-inversion identifications are predicted to generate four different return subcarrier signals. The above control is effective when a VTR is servo-controlled in such a way that the reproduced video signal is written in the buffer memory in advance of the reference video signal in phase.

Time base error corrector

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Kanagawa, Japan

Yasuo Sakura