Fujitsu Corporation

Yasuo Ohtomo

Nobukazu Koizumi

Kazuhiko Hatae

Masashi Sato

Daisuke Sasaki

Masato Oota

Yutaka Awata

Yuya Imoto

Mitsuo Kakuishi

Manabu Yamazaki

Tomoki Katou

Hisao Nakashima

Yoshitaka Nomura

A signal processing device includes: a memory; and a processor coupled to the memory and configured to: compensate an electric field signal representing an electric field component in an optical signal input from a transmission channel for an optical frequency offset between light sources on a transmission side and a reception side of the optical signal based on a compensation value; calculate an estimated value of the optical frequency offset from data having a fixed pattern in the electric field signal; generate a plurality of candidates for the compensation value from the estimated value; calculate power of the optical signal compensated for the optical frequency offset based on each of the plurality of candidates; and select an initial value of the compensation value from the plurality of candidates based on the power of the optical signal.

Signal processing device and transmission device

An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.

Adaptive equalization circuit and optical receiver

A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

Signal processing circuit and optical receiving device

An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.

Amplitude adjustment circuit, digital coherent receiver, and amplitude adjustment method

A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal.

Adaptive equalization circuit, digital coherent receiver, and adaptive equalization method

A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.

Signal processing apparatus, signal processing method, and signal processing system

A loop filter include: a register that stores a result of arithmetic operation performed on a complex signal and outputs the stored complex signal; a first multiplier that multiplies the complex signal output from the register and a predetermined coefficient; an absolute value judging unit that outputs a multiplier coefficient used to control such that the amplitude of the complex signal output from the register is held in a predetermined range; a multiplier that multiplies an output from the first multiplier and the multiplier coefficient; a second multiplier that multiplies an input signal and a value (1&#x2212;the predetermined coefficient); and an adder that adds an output from the multiplier to an output from the second multiplier and inputs a result of addition into the register.

Loop filter

A signal modulation method by an electronic device which includes a minimal reducing unit that minimally reduces an integrated signal returned to an adder from an integrator. The signal modulation method includes generating an added signal with the adder. The signal modulation method further includes generating a new integrated signal with the integrator by returning a previously self-generated and stored integrated signal to the adder, and by integrating the added signal generated by the adder. The signal modulation method further includes generating a new quantization signal with a quantizer by quantizing the new integrated signal generated by the integrator.

Signal modulation method, signal modulation apparatus, electronic device, and computer program product

A data receiving device for reproducing a received symbol from a received data signal, includes a timing recovery circuit for controlling a phase of sampling the received data signal, by using pre-cursor information, the timing recovery circuit produces sampling phase control information by eliminating a high frequency component for the pre-cursor information, accumulating eliminated output, comparing accumulated output with a positive or a negative threshold value and subtracting the threshold value from compared output. The data receiving device further includes a masking circuit for masking the sampling phase control information when no-signal data or frame is detected in the received data signal.

Data receiving device for reproducing a received symbol from a received

The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them. A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter.

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Yokohama, Japan

Yasuo Ohtomo