Kabushiki Kaisha Toshiba

Yasuo Naruke

Taira Iwase

Wataru Igarashi

Masamichi Asano

Makoto Segawa

Yoichi Suzuki

Akihiro Mishima

Thoru Mochizuki

Mitsuhiko Kosakai

An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device. The address signal output control circuit is supplied with an address output control signal as externally given as a control signal for the purpose of selecting said row selection line by taking control of said row addressing signal in order to perform the control process as described above.

Semiconductor memory device implemented with a test circuit

A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drain regions of the other of the pair of transistors by means of the local interconnect; and a pair of buried contacts formed by embedding a pair of conductive materials in a pair of second openings formed in the interlayer insulating film, the pair of second openings being arranged above an outer one of the pair of source/drain regions of each of the pair of transistors, the outer one of the pair of source/drain regions being exposed to the second openings.

Semiconductor device and method for producing same

Semiconductor device and method for producing the same

Semiconductor memory device

A manufacturing method of a mask-ROM of two-layered gate electrode structure is provided. With this method, a cell transistor having a first-layered gate is converted into the depletion type according to data to be stored in the following manner. That is, a first conductive layer is insulatively formed over a semiconductor substrate of a first conductivity type, a silicon nitride film is formed on the first conductive layer, a polysilicon film is formed on the silicon nitride film, the polysilicon film is patterned and then altered into a silicon oxide film so as to increase its volume, and the silicon nitride film is patterned with the silicon oxide film used as a mask to form windows for permitting impurity to be doped therethrough. Then, impurity for converting cell transistors into the depletion type according to data to be stored is doped from the windows into the substrate through the first conductive layer.

Mask-ROM manufacturing method that enhances integration density

A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

Semiconductor memory cells and semiconductor memory device employing the

Growing community of inventors

Kawasaki, Japan

Yasuo Naruke