G.d.s. Co., Ltd.

Other

General Research of Electronics, Inc.

Yasuo Nagazumi

C.d.s. Co., Ltd.

Kazuyoshi Imazeki

A RAKE combiner apparatus uses a charge transfer element, which can permit a high-precision RAKE receiver to be constructed by a simple circuit structure, has lower consumption power, can allow the finger number to be arbitrarily set within a range of up to the number of taps of the matched filter and can implement a highly efficient RAKE process. This RAKE combiner apparatus has at least one charge routing mechanism for receiving a group of charge signals in at least one time sequence, and transferring each of the input charge signals to at least two different kinds of routes in accordance with a separately supplied digital signal; at least one signal accumulation mechanism for executing signal accumulation by integrating the routed charge signals directly as charges or after subjecting the routed charge signals to predetermined signal conversion; and a RAKE controller for predicting a multi-path environment of communication paths associated with reception of the input charge signals, and supplying a digital signal for determining a transfer route of each of the input charge signals to the charge routing mechanism.

Rake combiner apparatus using charge transfer element

A random pulse type radar apparatus sends out as an output signal a spectrum spread radio wave including a pseudo random signal-less period and receives echoes in this signal-less period to thereby significantly reduce transmission peak power. The random pulse type radar apparatus comprises a transmitter for generating a hybrid type spectrum spread signal by simultaneously using two kinds of modulations which are phase shift keying modulation for selecting a phase of a transmission radio wave in accordance with a pseudo noise digital code and outputting the transmission wave, and time hopping modulation for stopping transmission of a radio wave at random in accordance with the pseudo noise digital code; a receiving unit for selectively detecting an echo of a transmission signal radio wave, generated by the transmitter, from a target with a time delay; at least one a common antenna unit for use both for transmission and reception or antenna units installed close to each other and respectively serving single functional units; and a reception control unit for stopping an action of the receiving unit in a time zone in which the transmitter is outputting radio waves in accordance with the time hopping modulation, whereby a spatial distribution of an intensity of an echo of a transmitted radio wave is measured through computation of a cross-correlation function of a transmission signal and a reception signal.

Random pulse type radar apparatus

A general purpose charge mode, analog operation circuit provides adder, multiplier, divider (D/A converter) and other functions using a single hardware configuration to be used in different modes. A two-dimensional lattice circuit including electrical charge transfer devices, each driven by charge transfer electrodes, all or a portion of which having structures allowing independent control, and a plurality of the electrical charge transfer devices adjacent to each other in the circuit are controlled successively with respect to the analog circuit charge signals to provide operation functions such as addition, multiplication, division, and sign inversion.

General purpose charge mode analog operation circuit

The object of the present invention is to obtain a charge domain signal filter by composing an digital filter circuit with analog/digital mixed circuit and by introducing the analog processing into the process of multiplication and addition consuming the most of the electric power so as to reduce the total power consumption. The present invention is composed of at least one AD converter; at least one reference charge supply unit; a coefficient supply unit for supplying coefficient signals; a plurality of DA converters acting in a charge domain for receiving digital signal outputs supplied from said AD converter and said coefficient signal supply unit, and for performing the multiplication type DA conversion using, as a reference signal, a reference charge packet generated by said reference charge supply unit; and one circuit of analog shift register composed of N stages of charge transfer devices.

Charge domain signal filter

A data supply method for performing exact operations by a number of operation units receiving a single signal as input is proposed; and a composition of a system provided with both the filter function and the AD conversion function using the same is also proposed. The system comprises a charge signal supply unit, which is a charge splitter composed of charge transfer devices for splitting a input charge signal into N signal charge parts, for supplying as input for said charge splitter S (S is an integer equal or superior to 2) series of source time series charge signals as a single time series signal by multiplexing the same by the time division multiplexing; and a demultiplexing mechanism for taking as respective inputs the N outputs from said charge splitter, and for separating multiplexed S series of time series charge signals contained in this input to convert them into an independent time series signals.

Parallel charge signal delivery system, and filtering AD converter using

A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by 'RAKE method' the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Matched filter acting in charge domain

A multiplier using a charge transfer device, broadly applicable to analog signal processing, digital-to-analog (D/A) conversion, or parallel image processing. The multiplier includes a charge transfer device with at least 8 independent potential wells arranged in a ring, and charge signal accumulators having at least one set of a plurality of independently controlled potential wells connected in serial to at least one of these potential wells on the ring.

Multiplier using charge transfer device

A systolic array processor is provided which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD or the like. The processor is composed of a plurality of signal processors for performing signal processings for a plurality of signals including an analog signal or signals supplied as input signals thereto and determining analog outputs, a shift register array or shift register mesh consisting of a plurality of shift registers, and a timing controller for controlling signal processings, arithmetic additions, shift operations and sequences in time of control for shift directions, of the shift registers. The shift register array or mesh includes analog shift registers having functions of performing the addition of input signals, and the analog outputs are supplied to the analog shift registers as one input signals thereof, respectively.

Systolic array processor

Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing digital/analog processing. A digital to analog converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.

Digital to analog converter using recursive signal dividing charge

Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing analog/digital processing. An analog to digital converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.

Analog-to-digital converter

The apparatus includes a plurality of groups of plural data paths which are connected in such a manner that each data path of one group intersects with one or more data paths of another or more data path groups. Each data path of each group is composed of a shift register and at least one of the data paths of each group transfer a signal imputed thereto in a different direction from at least one of the remaining data paths thereof when one of the shift registers thereof is operated. The plurality of data path groups are arranged such that each data path of one group shares with one or more data paths of another one or more groups one or more data lines at one of more positions of those data paths except end positions thereof, and the data path groups sharing at least one data line with one another effect transfer operation of a signal within one time interval independently allotted to each of the groups, thereby permitting the signal on the data line to be transferred in a direction designated for each data path group when each group has effected the transfer operation of a signal.

Apparatus for relocating spatial information for use in data exchange in

A fuzzy logic operation circuit for two inputs includes two identical charge coupled devices having at least first and second gate electrodes connected in parallel on an output side and floating gates provided to a transfer electrode on an input side. A comparison device compares charge detection signals from the floating gates with each other and selects an input signal of either the smaller or greater of the two inputs by the comparison output.

Fuzzy logic operation circuit utilizing charge coupled devices

A fuzzy computer includes a defuzzifier composed of charge coupled devices which intake and transfer a set of fuzzy data elements in parallel. Pairs of positive and negative gate electrodes are located transversely to the charge coupled devices. The gate electrodes in each pair differ in their effective area to the corresponding charge coupled devices and all the positive and negative electrodes are connected together in respective groups. Each of the positive and negative groups senses independently as an electronic signal, such as voltage, the sum of weighted charge value at each charge coupled device behind the electrodes, multiplying by the weighing factors which are determined by the effective area of each electrode. A total output is obtained as the difference of the output signals at the positive and negative electrode groups.

Fuzzy signal defuzzifier using charged coupled devices

A fuzzy logic operation circuit for two inputs includes two identical charge coupled devices having at least first and second gate electrodes connected in parallel on an output side and floating gates provided to a transfer electrode on an input side. A comparison device compares charge detection signals from the floating gates with each other and selects an input signal of either the smaller or greater of the two inputs by the comparison output. A fuzzy computer includes a defuzzifier composed of charge coupled devices which intake and transfer a set of fuzzy data elements in parallel. Pairs of positive and negative gate electrodes are located transversely to the charge coupled devices. The gate electrodes in each pair differ in their effective area to the corresponding charge coupled devices and all the positive and negative electrodes are connected together in respective groups. Each of the positive and negative groups senses independently as an electronic signal, such as voltage, the sum of weighted charge value at each charge coupled device behind the electrodes, multiplying by the weighing factors which are determined by the effective area of each electrode. A total output is obtained as the difference of the output signals at the positive and negative electrode groups.

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Tokyo, Japan

Yasuo Nagazumi