Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Yasuo Murakuki

Shunichi Iwanari

Hiroshige Hirano

Masahiko Sakagami

Takashi Miki

Kunisato Yamaoka

Yasushi Gohou

Tetsuji Nakakuma

Masayoshi Nakayama

Yoshiaki Nakao

Keita Takahashi

Akinori Shibayama

Kazuyuki Kouno

Takafumi Maruyama

Masanori Matsuura

Takanori Ueda

Yuriko Ishitobi

A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Nonvolatile semiconductor storage apparatus

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Nonvolatile semiconductor memory device

The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

Semiconductor memory device

A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region.

Semiconductor memory device and semiconductor integrated circuit

A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

Semiconductor memory device and semiconductor memory system

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cellin the memory corecorresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.

A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Ferroelectric memory and method for reading data from the ferroelectric memory

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell, in the memory core, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage areaformed from electrically-rewritable nonvolatile memory and a second setting function storage areaformed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address registerand transfer of operation mode setting information to an operation mode registerare selectively performed.

Semiconductor storage device

A semiconductor memory device includes memory cell blocks () through () including a nonvolatile memory cell. The memory cell blocks () through () include chip-data storing regions () through () for storing chip data containing operation parameters of the semiconductor memory device and pass-flag storing regions (11) through () for storing pass flags which correspond to the respective chip-data storing regions and show the validity of the stored chip data. The chip-data storing regions store the same chip data.

Semiconductor memory device and method for initializing the same

A semiconductor memory device having a semiconductor substrate includes a plurality of reference cellsand a plurality of bit lines. The reference cellsare formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines. The bit linesform pairs each composed of two adjacent bit lines. Two bit linesin each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lineshas at least one cross sectionwhere one of the pair of bit linescrosses the other, to switch between the first parallel state and the second parallel state. The cross sectionis provided in the predetermined region of the semiconductor substrate such that the length of a bit linein the first parallel state is equal to the length of the bit linein the second parallel state. The semiconductor memory device is reduced in size.

A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cellincluding a fuseis connected to a pair of bit lines of a memory circuit. The fuseand a fuse data output circuit (which includes a resistorand an inverter) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch. By allowing a column decoderfor selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

Semiconductor memory apparatus

A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

Ferroelectric memory device and method for reading data from the same

To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.

Growing community of inventors

Kyoto, Japan

Yasuo Murakuki