Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Renesas Device Design Corporation

Mitsubishi Electric Corporation

Agc Inc.

Yasuo Morimoto

Toshio Kumamoto

Takashi Okuda

Yoshihiro Funato

Kazuaki Kurooka

Yuko Maruyama

Takahiro Miki

Akimichi Hirota

Hideharu Yoshioka

Takeshi Motegi

Osamu Kagaya

Masao Ito

Naofumi Yoneda

Tomokazu Hamada

Akira Kumagai

Kazuaki Deguchi

Osamu Matsumoto

Masaki Fujiwara

Hiroyuki Kono

Motoshi Ono

Toshiki Sayama

Takashi Matsumoto

Takeshi Yuasa

Kazuhiko Niwano

Takuma Ishibashi

Kouichirou Takahashi

Keisuke Arai

Naoko Suwa

Nobuhito Shiraishi

Tsuyoshi Hatate

A semiconductor device includes a plurality of resistive films arranged on an interlayer dielectric film. Each of the plurality of resistive films extends in a first direction in plan view. The plurality of resistive films are arranged spaced apart in a second direction orthogonal to the first direction in plan view. The plurality of resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. A second width variation amount of each of the plurality of second resistive films belonging to the second group and a third width variation amount of each of the plurality of third resistive films belonging to the third group are larger than a first width variation amount of each of the plurality of first resistive films belonging to the first group.

Semiconductor device

An antenna device including a transparent antenna element that can be provided at a position visible from outside of a transparent cover of an electronic apparatus is provided. An antenna device includes a flexible substrate that is transparent and that is to be provided on an inner surface side opposite to an outer surface of a transparent cover, made of glass or resin, of an electronic apparatus, and an antenna element that is transparent and that is to be provided at a position, of the flexible substrate, that is visible from outside of the transparent cover, the antenna element having a directivity oriented toward an outside of the electronic apparatus.

Antenna device

A distributed antenna includes a strip member extending in a strip-like shape including a dielectric body of a plate shape having a first surface that is one surface of the dielectric body and a second surface that is opposite to the first surface; a transmission line provided on the first surface, on the second surface, or between the first surface and the second surface; and a plurality of antenna elements electrically connected to the transmission line and disposed in a distributed manner on the first surface or on the second surface, or electrically connected to the transmission line and disposed in a distributed manner between the first surface and the second surface.

Distributed antenna and distributed antenna system

An antenna includes an antenna conductor to be provided on an exterior side of a chassis and a flexible substrate. The flexible substrate includes a first insulating portion that is a portion of a sheet-shaped dielectric where the sheet-shaped dielectric is folded, a grounding conductor provided between the first insulating portion and the chassis, a second insulating portion that is a portion of the sheet-shaped dielectric where the sheet-shaped dielectric is not folded, and a signal line configured to feed power to the antenna conductor. A thickness of the first insulating portion is greater than a thickness of the second insulating portion.

Antenna

To obtain a downsized dielectric filter suitable for a laminating structure, a dielectric filter is configured with use of a dielectric waveguide formed of a conductor pattern and vias in a laminating direction within a multilayer dielectric substrate, two strip lines formed in a planar direction of the multilayer dielectric substrate, and two strip line-waveguide converters each configured to perform transmission line conversion between the dielectric waveguide and each strip line. In this manner, it is possible to provide a dielectric filter for which an area to be occupied in the planar direction of the multilayer dielectric substrate is suppressed.

Dielectric filter, array antenna device

Provided is a structure configured to electrically connect multi-layer dielectric waveguides, each including a dielectric waveguide formed of conductor patterns and vias in a laminating direction of the multi-layer dielectric substrate, in which the vias for forming part of a waveguide wall of each of the dielectric waveguides are arranged in a staggered pattern in the multi-layer dielectric substrate side having choke structures formed so as to electrically connect the waveguides to each other.

First and second dielectric waveguides disposed in respective multi-layer substrates which are connected by a connection structure having choke structures therein

A recess in a metal housing accommodating a high frequency package includes a first space and a second space and has a winners podium shape in cross-sectional view. A thermally conductive material is sandwiched between the metal housing having heat dissipating fins and the high frequency package.

Electromagnetic shield structure of high frequency circuit and high frequency module

According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.

Semiconductor device and electronic control system including the same

An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.

Analog to digital conversion circuit

A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.

An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n&#x2212;1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n&#x2212;1)-th.

During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.

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Tokyo, Japan

Yasuo Morimoto