Minolta Camera Kabushiki Kaisha

Funai Electric Company Ltd.

Hers Experimental Design Laboratory Inc.

Yasuo Masaki

Hiroshi Ueda

Manabu Murayama

Yuichiro Masuda

Kimitoshi Hori

Akira Yoshizaki

Chiaki Murata

Makoto Kawano

Hiroshi Uchino

Communication terminal

A processing circuit comprising a multiplying circuit, an ALU, a bit shift circuit, LUT, selectors, and constant registers can be adapted to various data processing as a whole processing circuit by appropriately changing the operation states of respective circuits and changing the setting of constant values. By combining a plurality of processing circuits, a data processing circuit capable of larger number of functions can be realized.

Digital image processing apparatus

A control circuit controls a hardware portion based on a microprogram set by a host CPU. Microinstructions constituting the microprogram comprise an instruction for setting an initial value of an address counter for reading microprogram as well as an instruction for controlling the hardware portion. The initial value setting instruction comprises an initial value setting instruction which uses the state of a flag register, which is set dependent on a change of state generated from the arithmetic processing in the hardware portion, as a condition. Therefore, the flow of reading of the microprogram can be changed corresponding to the change of the state generated by the arithmetic processing in the hardware portion.

An image data processing system comprising an image data input circuit, an image memory, an arithmetic logical circuit, an image data output circuit and a plurality of data buses, wherein the data buses include a first data bus to which the image data input circuit and the arithmetic logical circuit output data and from which the image memory and the image data output circuit input data and a second data bus to which the image data input circuit and the image memory output data and from which the arithmetic logical circuit and the image data output circuit input data. This image data processing system permits new direct data flows from the input circuit to the arithmetic logical circuit, from the input circuit to the output circuit and from the arithmetic logical circuit to the output circuit, in addition to conventional data flows from the input circuit or the arithmetic logical circuit to the image memory and from the image memory to the arithmetic logical circuit or to the output circuit.

Image data processing system

An image input circuit, an image memory, an image processing circuit and an image output circuit are controlled by a host CPU through a host CPU bus and are connected by an image data bus so as to enable data transfer between each other. The image memory, image processing circuit and the image data bus for multiple-valued image and those for binary image are prepared. Consequently, storing, processing and transfer of multiple-valued image data and those for binary image data can be carried out independently from each other.

A microprogram loaded in a microprogram memory by a host CPU is read out by a microprogram read control circuit in a vacant period existing in each cycle of operation of a hardware unit, whereby the microprogram is transmitted to each circuit of the hardware unit through a microprogram read-only bus. Each circuit of the hardware unit comprises a decoder and operation thereof is controlled based on a microinstruction decoded by the decoder.

Digital image processing apparatus having a microprogram controller for

Each of the processing circuits connected to an image data bus is adapted such that a delay of n transfer clocks (n is a positive integer) or an integer multiple thereof is generated between the input and output data. Therefore, the delay time of the whole processing circuit becomes an integer multiple of a fixed time period, no matter what pipeline structure is adopted to connect the processing circuits. An address counter connected to the image memory through an address bus delays one read address by a plurality of cascade connected delay circuits and outputs the same as write address with the output of respective delay circuit switched successively, so that it seemingly operates in the same manner as in the case where there are a number of write address counters.

Digital image processing apparatus for correctly addressing image memory

A plurality of registers for writing are connected to data input portions of respective memory devices and a plurality of registers for reading are connected to the data output portions thereof. A random access bus and a serial access bus are respectively connected to both of the registers for writing and the registers for reading. A control circuit controls the memory devices, registers for writing and the registers for reading to effect serial input/output control and random access control.

Image memory having plural input registers and output registers to

A camera for use with a disk film having a take lens window provided in the front side of a parallelepipedal housing closer to one lateral side thereof and a mirror device disposed at the center of the front side adjacent the window for observing the object. The mirror device is variable in its inclination to correct the parallax due to a variation in the distance of the object and has framing marks for indicating the field of view of the lens which differs with the object distance. The mirror device further has a coverage recognition sign which is observable only from a predetermined position within the coverage where an image of the object can be accurately observed on the device.

Growing community of inventors

Osaka, Japan

Yasuo Masaki