Matsushita Electric Industrial Co., Ltd.

Yasuo Kohashi

Masayoshi Tojima

Hitoshi Fujimoto

Hiromasa Nakajima

Shunichi Kuromaru

Tomonori Yonezawa

Masahiro Oohashi

Masatoshi Matsuo

Masayoshi Toujima

Toshihiro Moriiwa

Takashi Hashimoto

Shunichi Kurohmaru

Miki Arita

Kenichi Ishida

Tosihiro Moriiwa

Misako Matsumoto

The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main memory is connected to the first bus, and a frame memory is connected to the second bus. By the construction, a possible conflict in data transfer as 'urgent processing' and as 'normal processing' can be avoided. The data transfer as &#x201c;urgent processing&#x201d; includes transferring image data between the frame memory and an image input device or an image display device; while the data transfer as &#x201c;normal processing&#x201d; includes transferring image data between the main memory and the frame memory.

Integrated circuit, device and method for inputting/outputting images

The image processing apparatus according to the present invention comprises: DMA control meanshaving image input/output processing means, an external memory, DMA setting holding means, address generating means, DRAM control means, DMA request generating means, and DMA request adjusting means; a processorincluding encoding/decoding processing means; and a DMA busas shown in FIG. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.

Image processing device

The time required for access to a SDRAM () is extracted from the layout of an integrated circuit (), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit () is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit () in the designing stage is realized.

Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit

Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.

Video processing apparatus for performing address generation and control, and method therefor

A high-performance DMA controller for controlling data transfer between a main storage means holding various kinds of data and a plurality of local storage means, comprises: an interface for generating a control signal for the main storage means; a data I/O unit for controlling I/O of data; a parameter holding unit for holding various kinds of parameters that are required for execution of data transfer; a data transfer request receiver for receiving requests of data transfer; and a start command receiver for receiving a start/stop command of the data transfer controller. The data transfer request receiver receives, from a data transfer request source, reservations of plural data transfer requests comprising execution priority information and local storage means type information, each information being arbitrarily set by the data transfer request source, and holds the local storage means type information in association with each execution priority information. The data transfer controller receives only the reservations of data transfer requests until a start command is issued from a system controller and, when a start command is issued, the data transfer controller sequentially decodes the local storage means type information of the reserved data transfer requests having relatively high execution priorities, in chronological order of the data transfer requests, and then sequentially takes parameters required for data transfer from the parameter holding unit, according to the decoding result, to execute data transfer.

High-performance DMA controller

An object of the present invention is to provide an image processing apparatus in which a delay from start of image data input to start of coding is small, the capacity of a temporary storage device used for temporarily storing the image data to be coded is small, and the possibility of discarding the image data is low even when coding is delayed and, therefore, the image quality is hardly degraded. Since this apparatus is provided with a flag generator for generating control information according to the processing status, input/output of the image data in/from the temporary storage device is performed for each unit amount, and storage and coding of the image data are executed according to the control information.

Image processor and image processing method

In the case of using a database storing therein data on a plurality of circuits which are different in parameters such as circuit scale, memory capacity, number of pins, and operating frequency, the respective parameters of the circuits are analyzed automatically and a semiconductor integrated circuit device is designed automatically in accordance with the result of the analysis such that specifications required thereof are satisfied. For processor circuits, a micro-code and the like are analyzed automatically such that the processor circuits are improved or integrated. In the case of using block function IPs containing operations and circuit elements, a database storing therein IPs in a hierarchical configuration is used and a connecting portion between the internal functions of the IPs is withdrawn to the outside of the IPs, whereby a new IP or system is constructed.

Method of designing semiconductor integrated circuit device

In a host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller, the external host controller generates, as external addresses to be supplied to the connected device, first addresses corresponding to the respective internal addresses in an internal storage space of the connected device, and a specific second address corresponding to internal addresses of a series of areas in the internal storage space; and the host interface circuit includes a first address conversion circuit for converting the first addresses into the internal addresses in the internal storage space, and a second address conversion circuit for converting the specific second address into the internal addresses in the internal storage space; and the specific second address is used when the external host controller makes continuous access to the serial areas in the internal storage space of the connected device. Therefore, the external host controller can make continuous access to a series of areas in the internal storage space of the connected device by using the specific address, without using DMA, between the external host controller and the host interface circuit. As the result, power consumption is reduced, and complexity in software processing is reduced.

Host interface circuit

The time required for access to a SDRAM ( ) is extracted from the layout of an integrated circuit ( ), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit ( ) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit ( ) in the designing stage is realized.

Clock phase adjustment method, and integrated circuit and design method therefor

A conversion unit having a bidirectional conversion function of converting analog video signals into digital image data and vice versa and a processing unit having a function of encoding image data and of decoding encoded data are provided. A data transmission control unit switches the flow direction of each of image data and encoded data in response to an encoder/decoder switch signal. A process control unit performs switching of the receiving/transmitting of a control signal such as a transmission clock signal relating to encoded data in response to a master/slave set signal.

Image processor

A bus switch is connected among an input buffer memory, a data memory, and an encoding unit, to select between a first bus connection of the input buffer memory and the data memory and a second bus connection of the data memory and the encoding unit. A data transfer control unit controls the bus switch to select the first bus connection in response to a data request signal from the encoding unit, controls the process of reading from the input buffer memory and the process of writing into the data memory, controls the bus switch to select the second bus connection upon completion of the transfer of one unit of image data, and sends a transfer completion signal in order of causing the encoding unit to start performing encoding processing. This makes it possible to transfer image data from the input buffer memory to the data memory at high speed.

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Kasuya-gun, Japan

Yasuo Kohashi