Nihon Dempa Kogyo Co., Ltd.

Nihon Dempa Kogyo, Ltd.

Yasuo Kitayama

Naoki Onishi

Hiroki Kimura

Hiroyuki Demura

Nobuo Tsukamoto

Tsukasa Kobata

Tomoya Yorita

Shoichi Tsuchiya

A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.

Clock generating circuit and signal processing device

To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.

Signal level adjusting device and high-frequency apparatus

A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor Cis provided between a base of a driving transistor Qand GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil Lis provided on the emitter side of an oscillating transistor Q, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q, a resonance frequency in a resonant circuit having a capacitor Cand the coil Lis set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.

Low-noise voltage-controlled oscillating circuit

A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPFthat removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPFthat converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPFto that of the LPF; and a capacitor used for providing a capacitive coupling such that the output of the LPFis added to that of the LPF

VCO driving circuit and frequency synthesizer

A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

PLL circuit

A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.

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Chitose, Japan

Yasuo Kitayama