Sony Semiconductor Solutions Corporation

Sony Corporation

Yasuo Kanda

Yuji Torige

Mikio Oka

Takashi Yokoyama

Lui Sakai

Koichi Amari

Takayuki Arima

Shunsaku Tokitou

Yutaka Higo

Hiroyuki Uchida

Takafumi Kunihiro

Masahiro Segami

Kenji Noguchi

Keizo Hiraga

Shunsaku Tokito

A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.

Memory cell array unit

A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Semiconductor circuit including latch circuit for error correction

A semiconductor apparatus includes a nonvolatile memory cell array including a plurality of first memory cells and a plurality of second memory cells including a first memory elementand a second memory elementincluding a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory elementand the second memory element, in which a plurality of first memory elementsand a plurality of second memory elementsare arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on the same interlayer insulating layer, the first memory elementis larger than the second memory element, and the first memory elementand the second memory elementare disposed adjacent to each other along the second direction.

Semiconductor apparatus and method for manufacturing the same

A nonvolatile memory cell includes a resistance-change nonvolatile memory elementand a selection transistor TR. One end of the nonvolatile memory elementis connected to one source/drain regionA of the selection transistor TR and is connected to a write line WR. The other source/drain regionB of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory elementis connected to a bit line BL.

Nonvolatile memory cell, nonvolatile memory cell array, and information writing method of nonvolatile memory cell array

A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Semiconductor device and electronic apparatus including the same

A semiconductor circuit according to the present disclosure includes: a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film; a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.

Semiconductor circuit and electronic apparatus

Provided is a semiconductor device having a structure suitable for higher integration. The semiconductor device includes a transistor that includes a gate section, a first diffusion layer, and a second diffusion layer. The semiconductor device further includes a first electrically-conductive section a second electrically-conductive section that is electrically insulated from the first electrically-conductive section, a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section, and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Semiconductor device and imaging unit

A semiconductor circuit according to the present disclosure includes a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second nodes, a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node, a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal, a first transistor that couples the first node to the third terminal of the first memory element and a second transistor that is coupled to a first coupling node.

Semiconductor circuit and electronic device for storing information

A semiconductor circuit includes a first circuit to apply an inverted voltage of a voltage at a first node to a second node, a second circuit to apply an inverted voltage of a voltage at the second node to the first node, a first transistor that includes a gate, a drain, and a source, and stores a threshold state, a second transistor that couples the first node to a first terminal by being turned on, a third transistor that couples a first predetermined node to the gate of the first transistor, and a driving section that controls operations of the second transistor and the third transistor, and applies a control voltage to a second terminal. The first terminal is one of the drain or the source of the first transistor. The second terminal is another of the drain or the source of the first transistor.

Semiconductor circuit, driving method, and electronic device with less disturbance

A volatile logic circuit has a storage node, and stores inputted information. A plurality of non-volatile elements are connected to the storage node of the volatile logic circuit through the same connection gate, and control lines for control for these non-volatile elements are connected to the respective non-volatile elements, every non-volatile element. A plurality of non-volatile elements are connected to the volatile logic circuit through the same connection gate in such a way, thereby enabling the yield to be enhanced.

Semiconductor device having a volatile element and a plurality of non-volatile elements

A semiconductor circuit includes first (IV, IV) and second (IV, IV) circuits, first () and second () transistors, a first storage element (), and a driver (). The first (IV, IV) and second (IV, IV) circuits, respectively, apply inverted voltages of voltages at first (N) and second (N) nodes to the second (N) and first (N) nodes. The first transistor () is turned on to couple the first (N) and third nodes. The second transistor () includes a gate coupled to the first node (N), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL). The first storage element () includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element () is able to take a first or second resistance state. The driver () controls operation of the first transistor () and generates the first (SCL) and second (SCTRL) control voltages.

Semiconductor circuit, driving method, and electronic apparatus

A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.

The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Semiconductor storage device, driving method, and electronic device

A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Growing community of inventors

Kanagawa, Japan

Yasuo Kanda