Hitachi, Ltd.

Hitachi Appliances, Inc

Yasuo Kaminaga

Yoji Nishio

Tsutomu Yamada

Kenichi Kurosawa

Akihiro Ohashi

Kouji Masui

Yutaka Kobayashi

Akihiko Kanouda

Masataka Minami

Hiroyuki Shoji

Akihiro Tamba

Junpei Uruno

Isamu Kobayashi

Nozomi Horino

Kousaku Hirose

Yoshihiko Yamamoto

A unidirectional DC-DC converter and method of control thereof. The converter includes a DC power-supply, a buck converter circuit having a first main switching element, a boost converter circuit having a second main switching element, a first snubber capacitor, a first inversely-parallel diode, a control device, and an output diode.

Buck-boost DC-DC converter with auxiliary inductors for zero current switching

A unidirectional DC-DC converter which has a simple control circuit without using multiple insulated power supplies or a transformer, uses an auxiliary inductor of a comparatively small capacitance, reduces the size and weight of the converter, and has a very great capacitance without switching of supply current. For example, a unidirectional DC-DC converter equipped with main IGBTwhich supplies and shuts off current for first inductorand diodewhich discharges energy from main inductorto an the output. The DC-DC converter is further equipped with auxiliary IGBTwhich applies current to back-to-back-connected diodeby using energy stored in auxiliary inductorwhich is magnetically coupled with main inductor. This applies current to the back-to-back-connected diode in a short period including a time period in which the first switching element is turned on and accomplishes ZVZCS.

Unidirectional DC-DC converter

A soft switching DC-DC converter is provided which includes circuitry for both a buck converter and a boost converter. The buck converter circuitry and the boost converter circuitry share a common transformer including a primary coil and first and second secondary coils. A first switching element is coupled to a first capacitor to provide the buck converter operation while another switching element is provided to provide the boost converting operation. The primary coil of the transformer is commonly used as a choke coil by both the buck converter and the boost converter. In this way, size and cost reduction can be obtained.

Soft switching DC-DC converter including a buck converter and a boost converter sharing a common transformer

Input/output device for connection and disconnection of active lines

There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device,comprises an electronic circuit,and a MOS switch,and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device,two power supply systems, namely a stable power supply,and an unstable power supply,At the time of insertion or removal of the expansion device,power is provided to the MOS switch,and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch,in a high impedance state, inside the expansion device the high impedance maintaining circuit,drives an open/close control terminal, and power is provided to the electronic circuit,from the unstable power supply,At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.

In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.

Semiconductor gate array device

An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first voltage level Vcc1, whereby the noise resistance and the latch-up resistance of the input and output buffer circuit are improved while preventing a path current flowing through the driver PMOS transistor.

Input and output buffer circuit

The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form. This type of arrangement is used to effect a BiNMOS type of logic (inverter) circuit. In accordance with another structural scheme, in place of the first CMOS logic gate, a BiCMOS type of arrangement is effected in combination with the second CMOS logic gate and differentiator.

Semiconductor integrated circuit device comprising CMOS transistors and

The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

High-speed semiconductor integrated circuit device composed of CMOS and

The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.

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Hitachi, Japan

Yasuo Kaminaga