Kabushiki Kaisha Toshiba

Victor Company of Japan, Limited

Hokuriku Pharmaceutical Co., Ltd.

Other

Nec Corporation

Nippon Electric Co., Ltd.

Kabushiki Kasiha Toshiba

Yasuo Itoh

Yoshihisa Iwata

Masaki Momodomi

Tomoharu Tanaka

Hideo Kato

Riichiro Shirota

Yoshiyuki Tanaka

Fujio Masuoka

Seiichi Aritome

Hideko Odaira

Takashi Mori

Masamichi Asano

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Junichi Miyamoto

Eiichi Koshinaka

Ryouhei Kirisawa

Nobuaki Takahashi

Kazunori Ohuchi

Nobuo Ogawa

Masao Kasuga

Ryozo Nakayama

Masahiko Chiba

Koji Sakui

Sumio Tanaka

Mitsugi Ogura

Yoshiki Iwasaki

Kazuya Mitani

Shigeru Atsumi

Shinji Nakamura

Fumio Horiguchi

Shigeyoshi Watanabe

Yoshihisa Sugiura

Satoshi Inoue

Kazunori Nishikawa

Hiroyuki Nishino

Yasuhisa Okabe

Masaaki Satoh

Hideaki Ozaki

Shunichiro Sakurai

Katsuhiro Ohba

Koichi Toita

Tetsuo Endo

Tatsuo Sawada

Nobuhide Ohsaki

Nobuaki Suda

Kenichi Imamiya

Koji Hosono

Ken Takeuchi

Hiroshi Iwahashi

Tetsuo Endoh

Yukinobu Ishigaki

Hiroshi Nakamura

Kazuo Hikawa

Akiyoshi Hamanaka

Hiroyoshi Hidaka

Rikio Maruta

Teruo Muraoka

Kohei Sasamura

Isami Kaneda

Jun Sakaguchi

Tsuneo Furuki

Tomoyasu Nishikawa

Sakae Kurata

Atsushi Tomozawa

Toshihiko Yoshida

Toshio Tanaka

Tomio Suzuki

Kouji Morikawa

Yuisuke Maruyama

Kyojiro Sei

Noriyuki Yagi

Takehisa Yamada

Akira Hisano

Kugako Matsumura

Shigenori Tanaka

Kenichi Hara

Keiichi Yamamoto

Hikotaro Itani

Atsumu Yamane

Akio Kasama

Isao Suichi

Hiroyuki Kajioka

Kunimasa Sasaki

Toshie Yamauchi

Michiya Hayashida

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Non-volatile semiconductor memory device and memory system using the same

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCCand a ferro-electric capacitor DCC. One end of the paraelectric capacitor DCCand one end of the ferro-electric capacitor DCCare commonly connected to a node N. A dummy plate electric potential DPLis supplied to the other end of the paraelectric capacitor DCC, and a dummy plate electric potential DPLis supplied to the other end of the ferro-electric capacitor DCC. When data of a memory cell MC is read at a bit line (selective bit line) BL, a reference electric potential is supplied to a bit line (reference bit line) BLfrom the dummy cell DC.

Ferro-electric random access memory using paraelectric and ferroelectric capacitor for generating a reference potential

A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

Nonvolatile semiconductor memory device having verify function

There is provided an internal voltage generating circuit for outputting positive multi-level voltages by using a current addition type D/A conversion circuit, and suppressing increase of the pattern area of a resistor network even if the number of bits of a digital input increases. This circuit includes a load resistor element having one terminal connected to the output node of a voltage generating circuit, a first voltage setting circuit which is connected to a first node to which the other terminal of the load resistor element is connected and controls the magnitude of an input current from the load resistor element by controlling an equivalent resistor in accordance with digital data, a second voltage setting circuit which is connected to the first node and into which a predetermined current flows from the load resistor element, a potential comparison circuit for detecting a potential at the first node by comparing the potential at the first node with a reference potential, and a voltage control circuit for setting the potential at the first node to become equal to the reference potential by substantially controlling the voltage generating circuit in accordance with an output from the circuit.

Internal voltage generating circuit capable of generating variable multi-level voltages

An internal voltage generator generates an internal voltage that is obtained by up-converting or down-converting an external power supply voltage. A resistor-voltage divider, having a plurality of resistors, outputs a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors. A capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, outputs a second divided voltage from the capacitors. A comparator compares a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison. The comparator judges whether to halt operation of the internal voltage generator or not based on the result of comparison between the reference voltage and the first divided voltage while the internal voltage generator is operating. On the other hand, the comparator operates the internal voltage generator based on the result of comparison between the reference voltage and the second divided voltage while the internal voltage generator is not operating. The comparator further controls the resistor-voltage divider so that a current flows therethrough only when the internal voltage generator is operating.

Semiconductor device

Non-volatile semiconductor memory device with an improved verify voltage generator

In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

Non-volatile semiconductor memory device

A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

Electrically erasable programmable read-only memory with threshold value

A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

Variable potential generating circuit using current-scaling adding type

A semiconductor memory device includes a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable, a select gate connected to a select gate line for connecting a memory cell unit to a bitline, a precharge circuit connected to a first node of the bitline, for supplying a precharge voltage higher than an power supply voltage in programming of data, and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage in programming of data.

Semiconductor memory device

The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied. The control circuit controls the dividing circuit such as to set the write voltage indicated by the write voltage data in the memory element in the write mode. Thus, the write voltage is optimized, and the appropriate number of times of write can be performed.

Growing community of inventors

Kawasaki, Japan

Yasuo Itoh