Nec Corporation

Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Japanese National Railways

Nihon Biso Kabushiki Kaisha

Yasuo Ishii

Michio Fujiwara

Yohei Yamada

Takashi Kurokawa

Toshikazu Aoyama

Teruyuki Imai

Yoshio Akutsu

Masujiro Matsuo

Sigeru Ogawa

Schun'ichi Itoh

Akoi Otani

Daisuke Takei

Harumi Nagasawa

An electronic circuit includes: an arithmetic processing part executing given arithmetic processing; and a capacitor supplying accumulated electric charge when the arithmetic processing part executes arithmetic processing. The arithmetic processing part operates by using the electric charge supplied from the capacitor.

Electronic circuit, arithmetic processing control method, program, and multi-core processor

The present invention resolves the problems of OS jitter and cache pollution, as well as the loss of versatility and increases in development cost. An information processing apparatus includes a control core on which an operating system is installed, and at least one calculation core which is controlled by the control core and performs a predetermined calculation process. The control core includes calculation core control unit for instructing the calculation core in halting, to start the calculation process to be performed by calculation core. The calculation core includes calculation processing control unit for controlling the calculation core so as to start the calculation process in response to an instruction, provided by the calculation core control unit, about starting the calculation process, and exception detection unit for detecting a preset exception process occurring during execution of the calculation process and halting the calculation process in which the exception process has occurred.

Information processing device, information processing method, recording medium, calculation processing device, calculation processing method

In a multi-core processor having a plurality of processor cores, each of the processor cores is configured to calculate consumed energy on a basis of issued instruction information and power consumption information. The consumed energy is energy consumed in execution of an instruction issued by the processor core. The issued instruction information represents the instruction issued by the processor core. The power consumption information represents change of power consumption resulting from execution of processing corresponding to the instruction.

Multi-core processor, information processing method, and program

A flush control apparatus controls a Set Associative cache memory apparatus. A flush control apparatus includes: a tag memory unit associating a tag identifier identifying a tag which associates a plurality of cache lines and tag information representing whether or not the tag is valid. It also includes a line memory unit, a way specification unit and a flush unit which flushes the way specified by the way specification unit.

Flush control apparatus, flush control method and cache memory apparatus

A branch prediction device capable of preventing degradation of branch prediction accuracy and a delay in processing speed is provided. The branch prediction device includes a branch prediction information accumulation processing section which stores branch prediction groups in which a plurality of pieces of branch prediction information are grouped, and performs accumulation-processing of the branch prediction information. The branch prediction device further includes a pipeline access control section which performs processing, upon request, by pipeline processing, including first selection control processing for selection-controlling at least one branch prediction group from the branch prediction groups, and second selection control processing for selection-controlling one or a plurality of pieces of branch prediction information from the branch prediction group, and controls an access to the branch prediction information accumulation processing section.

Branch prediction device and method that breaks accessing a pattern history table into multiple pipeline stages

A scaffolding system for performing a work such as repair, coating or tiling on an outer wall surface of a building, chimney, petroleum tank or the like comprises parapet wall hooks provided on the top portion of a building, hanging stages suspended from the parapet wall hooks by means of first cables and arranged in horizontal alignment with one another, protective nets which can be stretched between the parapet wall hooks and the hanging stages, and means for lifting and lowering the protective nets by means of second cables secured to the protective nets. The protective nets can be lifted or lowered as desired regardless of position of the hanging stages and without lifting or lowering the hanging stages. The protective nets can be readily lowered and stored in the hanging stages when a strong wind is expected whereby damage to the protective nets due to wind can be prevented.

Scaffolding system for performing a work on an outer wall surface of a

An ac type line concentrator for use in a data communication system, comprising a crosspoint switch circuit. The crosspoint switch circuit is constituted by a plurality of crosspoint switches capable of switching an analog signal (hereinafter referred to as an analog switch), so that a carrier signal modulated by a data signal may be transferred from one of m incoming lines connected with m terminal units to a selected one of n(n&lt;m) outgoing lines connected with a central unit through the ac type line concentrator without being demodulated.

Growing community of inventors

Tokyo, Japan

Yasuo Ishii