Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Yasuo Igura

Eiji Takeda

Hitoshi Kume

Hideyuki Matsuoka

Tokuo Kure

Akihiro Shimizu

Toru Kaga

Atsushi Hiraiwa

Masatada Horiuchi

Takaaki Hagiwara

Ryuichi Izawa

Toshiyuki Yoshimura

Shimpei Iijima

Akemi Hamada

Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

Transistor with overlapping gate/drain and two-layered gate structures

A semiconductor field effect transistor is provided which permits controlling of the phase of carriers between a source region and a drain region formed in a first semiconductor layer. Such control can be used to modulate characteristics such as the electric conductivity and drain current of the transistor. To accomplish this control, a gate electrode is formed over a portion of said first semiconductor layer between the source and drain regions. The gate electrode splits to form first and second branches at a first location adjacent to the source region. These first and second branches subsequently rejoin one another at a second location adjacent to said drain region. When a potential is applied to the gate electrode, it will produce first and second two-dimensional carriers conduction paths at a surface of the portion of the first semiconductor layer under the first and second branches. An arrangement is provided for modifying the phase of carriers passing through the first conduction path relative to the phase of carriers passing through the second conduction path to produce a phase difference for carriers received at the drain region through said first and second conduction paths.

Semiconductor device with a split conduction channel

In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading. A memory cell capable of extremely large scale integration can be obtained.

Stacked semiconductor memory

Growing community of inventors

Kawasak, Japan

Yasuo Igura