Fujitsu Corporation

Credo Technology Group Limited

Yasuo Hidaka

Weixin Gai

Junqing (Phil) Sun

Hirotaka Tamura

Yoichi Koyanagi

Junqing Phil Sun

Jian Hong Jiang

Pradip Thachile

An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error; and a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.

Clock recovery with loop delay cancellation

An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board ('PCB') trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

Serdes equalization for short, reflective channels

An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.

Second-order clock recovery using three feedback paths

SerDes equalization for short, reflective channels

A method of computing includes defining a first atomic random variable (ARV) and first random variable (RV) in a programming language system. The first ARV having a non-deterministic value of either zero according to a second probability or one according to a first probability. A sum of the first probability and the second probability is one. A covariance of the first ARV and a second ARV is zero. The first RV has a first indefinite value at a first definite probability and includes a polynomial of one or more atomic random variables (ARVS) that includes the first ARV. The method includes executing a computer instruction that includes a mathematical operation involving the first RV as a basic data type and produces a second RV having a second indefinite value at a second definite probability, represents a result distribution, and tracks a response to the one or more ARVS.

Computing using unknown values

A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

Compensating for intra-pair skew in differential signaling

A method of selecting filter patterns is provided. The method may include measuring an average sign value of aggregate inter-symbol interference (ISI) for a data sequence using multiple filter pattern combinations of multiple filter patterns; estimating a first analog level of aggregate ISI for a first filter pattern based on a first average sign value, and a second analog level of aggregate ISI for a second filter pattern based on a second average sign value; estimating an analog level of individual ISI of the first filter pattern pair based on the first analog level and the second analog level; estimating, for each possible filter pattern combination, an analog level of aggregate ISI for the first filter pattern pair; and selecting a filter pattern combination for the first filter pattern pair that reduces the analog level of aggregate ISI.

Sign-based adaptive control with automatically-selected filter patterns

A circuit may include a signal path, a first layer including the signal path, and a second layer including the signal path. The circuit may additionally include a path via having a signal-path via location and configured to connect the signal path at the first layer with the signal path at the second layer. The circuit may also include a ground plane associated with the first layer. The ground plane may have a ground-plane location that corresponds to the signal-path via location. The ground plane may also include an asymmetrical cutout portion that extends away from the ground-plane location on a first side of the ground plane that is opposite a second side of the ground plane that corresponds with a side of the first layer where the path via interfaces with the signal path at the first layer.

Electromagnetic field manipulation around vias

A circuit may include a differential via that may include a first via having a first-via length and a second via having a second-via length longer than the first-via length. The circuit may also include a differential stripline coupled to the differential via. The differential stripline may include a first trace and a second trace that are broadside coupled to each other over at least a portion of the differential stripline to form a broadside coupled portion of the differential stripline. The first trace may be coupled to the first via and may have a first-trace length. The second trace may be coupled to the second via and may have a second-trace length. The broadside coupled portion of the differential stripline may be offset from a plane intersecting substantially half-way between the first via and the second via such that the second-trace length is shorter than the first-trace length.

Compensation for length differences in vias associated with differential signaling

A method includes, by a detector, receiving from a low frequency equalizer a data signal and an error signal, matching a tail portion of the data signal to a tail portion of an extended filter-pattern, and, based upon the error signal at a given location of the data signal and upon the imbalance, producing an output signal indicating whether a long-term residual intersymbol interference of the data signal in the error signal has a positive sign or a negative sign. The tail portion of the extended filter-pattern includes an imbalance between a count of each of the possible values and an unfixed sequence. The data signal includes data points with one of at least two possible values.

Adaptive control of low-frequency equalizers

In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals.

Analog continuous-time phase equalizer for data transmission

The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Optimized via cutouts with ground references

A method of compensating for loss of a high-speed broadband signal may include receiving a high-speed broadband signal. The method may also include at least partially compensating for a low-frequency loss associated with a low-frequency component of the high-speed broadband signal. The compensation for the low-frequency loss may be based on a transfer function that may include a pole with a pole-frequency associated with the low-frequency component of the high-speed broadband signal.

Low-frequency equalizer circuit for a high-speed broadband signal

In particular embodiments, a method includes generating by a data detector a recovered data signal from a phase-equalized signal based on the transmitted data in the phase-equalized signal; comparing by a phase-distortion detector the phase-equalized signal and the recovered data signal with each other; based on the comparison, determining by the phase-distortion detector a phase-distortion level; generating by the phase-distortion detector a phase-distortion-level signal based on the phase-distortion level; generating by an integrator a phase-equalize-level signal based on the phase-distortion-level signal; and adjusting by a phase equalizer a transmitted-data signal based on the phase-equalize-level signal, the adjustment of the transmitted-data signal providing the phase-equalized signal or a phase pre-distorted signal configured to be distorted into the phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising the transmitted data.

Growing community of inventors

Cupertino, CA, United States of America

Yasuo Hidaka