Mitsubishi Electric Corporation

Mitsubishi Electronic Corporation

Yasuo Ata

Tsuyoshi Osaga

Tetsujiro Tsunoda

Hideki Haruguchi

Tomohito Kudo

Takahiro Okuno

Koichiro Kisu

Shinichi Tabuchi

Yoshihumi Tomomatsu

A semiconductor device includes a semiconductor substrate, an effective region formed as a conductive section on the semiconductor substrate, an ineffective region formed as a non-conductive section on the semiconductor substrate, a wiring metal formed in the effective region, a metal section provided on an upper surface of the wiring metal and exposed to an outside, an identifying mark provided on the upper surface of the wiring metal and exposed to the outside, the identifying mark being spaced apart from the metal section, and an insulating body provided on the upper surface of the wiring metal and exposed to the outside, the insulating body being adjacent to the metal section and the identifying mark.

Semiconductor device, and method for manufacturing semiconductor device

A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

Semiconductor device, semiconductor wafer and method for manufacturing semiconductor device

A semiconductor device includes, on an upper surface side of an N-type drift layer, a P-type well layer, an N-type emitter layer, a gate insulation film, and a gate electrode, and includes, on a lower surface side of the N-type drift layer, an N-type buffer layer, a P-type collector layer, and an N-type layer. The N-type layer is partially formed in the N-type buffer layer. The N-type layer has impurity concentration being higher than impurity concentration of the N-type buffer layer and being equal to or higher than impurity concentration of the P-type collector layer.

Semiconductor device

A back surface of a wafer is formed with a ring-shaped projecting portion. The wafer is cut with a blade from a side of a front surface of the wafer in a state where the projecting portion of the wafer with a back surface facing upward is supported.

Semiconductor manufacturing method for cutting a wafer

A third dummy trench () is orthogonal to the first and second dummy trenches () in the dummy cell region of a substrate end portion. An interlayer insulating film () insulates the p-type diffusion layer () in the dummy cell region of a substrate center portion situated between the first and second dummy trenches () from the emitter electrode (). The third dummy trench () separates the p-type diffusion layer () in the dummy cell region of the substrate center portion from the p-type diffusion layer () in the dummy cell region of the substrate end portion connected to the emitter electrode (). A p-type well layer () is provided deeper than the third dummy trench () in the substrate end portion. The third dummy trench () is provided closer to a center of the n-type substrate than the p-type well layer ().

Semiconductor device including active and dummy cell regions

A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.

Growing community of inventors

Tokyo, Japan

Yasuo Ata