Nec Corporation

Kabushiki Kaisha Toshiba

Nippon Electric Co., Ltd.

Yasuo Akatsuka

Masahiro Takagi

Hiroshi Tsurumi

Koji Horisaki

Takashi Nakada

Kojiro Suzuki

Toshihiro Nakamura

A display apparatus includes a plurality of surfaces, and a display device provided on at least one surface among the plurality of surfaces. A plurality of communication sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces and configured to perform communication within a predetermined distance, each of the plurality of communication sections including different identification information. A control section is configured to perform control of the plurality of communication sections and the display device. When another display apparatus is connected to the display apparatus, the control section periodically performs time synchronization to synchronize an image displayed on the display device with an image displayed on a display device provided in the other display apparatus.

Display apparatus and display system

According to an embodiment, a display block is a display apparatus including a plurality of surfaces. The display block includes a display device, a plurality of transmitting/receiving sections that perform communication within a predetermined distance, and a control section. The display device is provided on at least one surface of the plurality of surfaces. The plurality of transmitting/receiving sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces. The control section performs control of the plurality of transmitting/receiving sections and the display device.

A static memory circuit which can stably conduct a write operation with large margins is disclosed. The memory circuit comprises a plurality of static type memory cells, a first terminal for receiving input data to be written, a second terminal for receiving a control signal for changing an operation mode of the memory from a read operation mode to a write operation mode, a latch circuit for holding the input data during the write operation mode, and circuitry for applying the held data by the latch circuit to a selected memory cell.

Static memory including data buffer and latch circuits

A CMOS integrated circuit formed in a first semiconductor substrate is supplied with a power through a power control circuit formed in a second semiconductor substrate. The power control circuit is, for example, a flip-flop using the CMOS integrated circuit as one load and detects that a resistance value of the one load is decreased below a predetermined value and decreases power supplied to the CMOS integrated circuit in response to the detection.

CMOS integrated circuit protected from latch-up phenomenon

An improved memory circuit having power-down mode is disclosed. The memory is of the type having a memory cell matrix and a peripheral circuit for achieving access operation to the memory cell matrix under control of at least one control signal and is featured in that a power supply to at least a part of the peripheral circuit is stopped only when the control signal is kept inactive for a predetermined period or more, reducing the power consumption in the memory.

Memory circuit with improved power-down control

A memory device operable at high speed is disclosed. The device comprises selection means coupled to word lines for selecting one of them detection means for detecting a signal appearing in the selected word line, and word line drive means responsive to an output of the detection means for supplying the selected word line with a voltage capable introducing a selection level in it independent on the selection means.

Memory device

An integrated circuit operable with low power consumption and high reliability is disclosed. The circuit comprises a logic circuit receiving an input logic signal at its input, detection means for detecting a change in the logic input signal, means responsive to an output of detection means for producing a control signal, and control means responsive to the control signal for setting the logic circuit at a predetermined condition irrespective of the input logic signal.

Growing community of inventors

Tokyo, Japan

Yasuo Akatsuka