Kabushiki Kaisha Toshiba

Yasunori Usui

Hidetoshi Nakanishi

Shigeo Kouzuki

Hideo Matsuda

Takashi Fujiwara

Shigenori Yakushiji

Takuma Hara

Takeshi Uchihara

Hiroshi Okamura

Masaru Izumisawa

Takahiro Kawano

Yoshihiko Saito

Hideyuki Ura

Masaru Ando

Tatsuo Yoneda

Shinjiro Kojima

Yoshinari Uetake

Yoshiaki Tsunoda

Akira Tanioka

Shinjiro Yano

Keinichi Tokano

In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

MOSFET

As and B are implanted to side surfaces of trenchesby a rotation ion implanting method, and by using a difference between these impurities in diffusion coefficient, the structure in which an n-type epitaxial Si layer is interposed between trenchesis converted into a semiconductor structure consisting of n-type pillar layer/p-type pillar layer/n-type pillar layerlining up. The structure can function substantially the same role as that of a super junction structure.

Vertical type semiconductor device and method of manufacturing the same

According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second impurity concentration, an insulating film formed over the surfaces of the first, second, third, and fourth semiconductor layers, and a control electrode formed on the insulating film, wherein a junction of first and second conductivity types formed between the first semiconductor layer and the third semiconductor region is positioned below the control electrode, or below an end portion, on a side of the third semiconductor region, of the control electrode, via the insulating film.

Semiconductor device

A semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type juxtaposed on a semiconductor substrate of the first conductivity type. The first semiconductor layer has an impurity concentration lower than that of the semiconductor substrate. The second semiconductor layer has at a central location a trench, which extends from the upper end toward the semiconductor substrate. A first region of the second conductivity type is formed to include an upper portion of the second semiconductor layer. A second region of the first conductivity type is formed in a surface of the first region. A gate electrode is disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the first semiconductor layer.

Semiconductor device and manufacturing method thereof

A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75&lE;DT/WP&lE;60 or 5.5&lE;DT/WTmin&lE;14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Power MOSFET having laterally three-layered structure formed among element isolation regions

On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

MOS gate controlled thyristor

On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

A P type source region is formed in a grid mesh-like pattern in one major surface portion of an N.sup.- type semiconductor substrate. A P type base region and P.sup.- type base region are each formed in the one major surface portion of the N.sup.- type semiconductor substrate at an area between those grid mesh-like portions of the P type source region. An N type emitter region is formed in the P type base region. An N type emitter region is formed in the P.sup.- type base region. A gate electrode is formed over the P type source region, N.sup.- type semiconductor substrate, P type base region and P.sup.- type base region. The gate electrode is formed in a grid mesh-like pattern as viewed from above the N.sup.- type semiconductor substrate. A cathode electrode is contacted with the P type source region, P.sup.- type base region and N type emitter regions. A P.sup.+ type emitter layer is formed on an other major surface side of the N.sup.- type semiconductor substrate. An N.sup.+ type buffer layer is formed between the N.sup.- type semiconductor substrate and the P.sup.+ type emitter layer. An anode electrode is contacted with the P.sup.+ type emitter layer. A cell acts as a switch at a turn-on time and a resultant MCT is rapidly turned on. Those cells .alpha. and .beta. have such an arrangement as to improve the turn-off characteristic.

Disclosed is a semiconductor device comprising an output Triode AC switch with a vertical structure, which is provided in a silicon substrate and has a gate, a first output terminal and a second output terminal, and an input/driving photo Triode AC switch, which is provided in the substrate and has a light-receiving portion, a first terminal connected to the gate and a second terminal connected to the second output terminal. The output Triode AC switch with a vertical structure is turned on when light is input to the photo Triode AC switch.

Light triggered triac device and method of driving the same

A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

MOS gate controlled thyristor having improved turn on/turn off

A soft metal plate having substantially equal hardness as emitter electrodes formed of soft metal is disposed between the emitter electrodes and a heat buffer metal plate formed of hard metal, and pressure applied to the emitter electrodes is shared by the soft metal plate, so as to reduce the thermal fatigue of the emitter electrodes.

Press-contact type semiconductor device

In a power semiconductor device according to the present invention, a sheet, formed of a soft metal such as Ag, is provided on that portion of a pressing control electrode which is brought into contact with an Al gate electrode of a pellet. By means of this sheet, it is possible both to apply a strong pressing power to the Al gate electrode and to reduce the contact resistance between the two electrode. Since an excessive amount of heat is not produced on account of the contact resistance, the semiconductor device can be protected against being damaged.

Power semiconductor device

A semiconductor device has a main GTO thyristor section, an auxiliary GTO thyristor section and a MOS transistor section. The main GTO thyristor section is turned on and off in accordance with a gate signal supplied to its gate terminal. The auxiliary GTO thyristor section supplies an igniting signal to the gate of the main GTO thyristor in accordance with an optical signal. The MOS transistor supplies an extinguishing signal to the gate of the main GTO thyristor section in accordance with an optical signal supplied to it.

Growing community of inventors

Yokohama, Japan

Yasunori Usui